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ZHCSDQ5A April 2015 – May 2015 LMH6401

PRODUCTION DATA.

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機械數據 (封裝 | 引腳)

RMZ|16
- MPQF431A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V = (VS+) – (VS–)		5.5	V
Digital input pins		–0.3	VS+	V
Maximum input difference voltage			2.1	V
Maximum input voltage		VS–	VS+	V
Temperature	Maximum junction, T_J		150	°C
	Maximum junction, continuous operation, long-term reliability		125	°C
	Operating free-air, T_A	–40	85	°C
	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Supply voltage	4.0	5.0	5.25	V
Minimum operating positive (VS+) supply voltage	2.0			V
Ambient operating air temperature, T_A	–40	25	85	°C
Operating junction temperature, T_J	–40		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMH6401	UNIT
		RMZ (UQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	78	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	43	°C/W
R_θJB	Junction-to-board thermal resistance	24	°C/W
ψ_JT	Junction-to-top characterization parameter	2.3	°C/W
ψ_JB	Junction-to-board characterization parameter	24	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

At T_A = 25°C, VS– = –2.5 V, VS+ = 2.5 V, VOCM = 0 V, R_LOAD = 200-Ω differential (R_o_{(internal, diff)} = 20 Ω), V_O = 2 V_PPD, and A_V = 26 dB, unless otherwise noted.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT	TEST LEVEL⁽¹⁾
DYNAMIC PERFORMANCE
SSBW	Small-signal, –3-dB bandwidth	A_V = 26 dB, V_O = 200 mV_PPD			4.5		GHz	C
LSBW	Large-signal, –3-dB bandwidth	A_V = 26 dB, V_O = 2.0 V_PPD			4.5		GHz	C
	Bandwidth for 0.1-dB flatness	A_V = 26 dB, V_O = 2.0 V_PPD			500		MHz	C
SR	Slew rate	V_O = 2-V step			18200		V/µs	C
t_R, t_F	Rise and fall time	V_O = 2-V step, 10% to 90%			82		ps	C
	Overdrive recovery	Overdrive = ±0.5 V			600		ps	C
	Output balance error	f = 1 GHz			–47		dB	C
t_s	Settling time to 1%	V_O = 2-V step, R_L= 200 Ω			700		ps	C
HD2	Second-harmonic distortion	f = 200 MHz, V_O = 2.0 V_PPD			–73		dBc	C
		f = 500 MHz, V_O = 2.0 V_PPD			–68		dBc	C
		f = 1 GHz, V_O = 2.0 V_PPD			–63		dBc	C
		f = 2 GHz, V_O = 2.0 V_PPD			–58		dBc	C
HD3	Third-harmonic distortion	f = 200 MHz, V_O = 2.0 V_PPD			–80		dBc	C
		f = 500 MHz, V_O = 2.0 V_PPD			–72		dBc	C
		f = 1 GHz, V_O = 2.0 V_PPD			–63		dBc	C
		f = 2 GHz, V_O = 2.0 V_PPD			–54		dBc	C
OIP2	Output second-order intercept point	f = 200 MHz, P_O = –2 dBm per tone			67		dBm	C
		f = 500 MHz, P_O = –2 dBm per tone			65		dBm	C
		f = 1 GHz, P_O = –2 dBm per tone			60		dBm	C
		f = 2 GHz, P_O = –2 dBm per tone			52		dBm	C
OIP3	Output third-order intercept point	f = 200 MHz, P_O = –2 dBm per tone			43		dBm	C
		f = 500 MHz, P_O = –2 dBm per tone			40		dBm	C
		f = 1 GHz, P_O = –2 dBm per tone			33		dBm	C
		f = 2 GHz, P_O = –2 dBm per tone			27		dBm	C
IMD2	Second-order intermodulation distortion	f = 500 MHz, V_O = 1.0 V_PP per tone			–68		dBc	C
IMD3	Third-order intermodulation distortion	f = 500 MHz, V_O = 1.0 V_PP per tone			–83		dBc	C
P1dB	1-dB compression point	f = 500 MHz, power measured at amplifier output			18.3		dBm	C
NF	Noise figure	R_S = 100 Ω	f = 200 MHz		7.7		dB	C
NF	Noise figure	R_S = 100 Ω	f = 1 GHz		8		dB	C
	Output-referred noise voltage	A_V = 26 dB, f > 1 MHz			30.4		nV/√Hz	C
S12	Reverse transmission (S12)	f = 1 GHz			–65		dB	C
S11	Input return loss (S11)	100-Ω system, f = 2 GHz			–15		dB	C
GAIN PARAMETERS
	Maximum voltage gain			25.5	26.0	26.5	dB	A
	Minimum voltage gain			–7.5	–6.0	–4.5	dB	A
	Gain range				32		dB	C
	Gain step size			0.9	1	1.1	dB	A
	Cumulative gain error	A_V = 26 dB to 10 dB (referenced to 26-dB gain)		–0.5		0.5	dB	A
	Cumulative gain error	A_V = 26 dB to –6 dB (referenced to 26-dB gain)		–1		1	dB	A
	Gain step transition time				1		ns	C
ANALOG INPUT CHARACTERISTICS
R_i	Input resistance	Differential		85	100	112	Ω	A
C_i	Input capacitance	Differential			0.8		pF	C
V_ICM	Input common-mode voltage	Self-biased to mid-supply		–0.3		0.3	V	A
V_ICLR	Low-level input common-mode voltage range	Differential gain shift < 1 dB			(VS–) + 1.5		V	C
V_ICHR	High-level input common-mode voltage range	Differential gain shift < 1 dB			(VS+) – 1.5		V	C
ANALOG OUTPUT CHARACTERISTICS
R_o	Output resistance	Differential		18	20	25	Ω	A
V_OL	Low-level output voltage range	Low-level clipping level			(VS–) + 1	(VS–) + 1.1	V	A
V_OH	High-level output voltage range	High-level clipping level		(VS+) – 1.1	(VS+) – 1		V	A
V_OM	Maximum output voltage swing	Differential			6.0		V_PPD	C
CMRR	Common-mode rejection ratio	±0.3-V input common-mode shift		38.4	45		dB	A
POWER SUPPLY
V_S	Supply voltage [V = (VS+) – (VS–)]			4.0	5.0	5.25	V	A
	Minimum positive (VS+) supply voltage			2.0			V	A
PSRR	Power-supply rejection ratio	VS–, measured at 1-kHz sine-wave		66	70		dB	A
PSRR	Power-supply rejection ratio	VS+, measured at 1-kHz sine-wave		66	70		dB	A
I_Q	Quiescent current	PD = 0 (device enabled)		60	69	78	mA	A
I_Q	Quiescent current	PD = 1 (device disabled)		1	7	12	mA	A
OUTPUT COMMON-MODE CONTROL (VOCM Pin)
SSBW	Small-signal bandwidth	VOCM = 200 mV_PP			160		MHz	C
	VOCM voltage range low	VOCM gain < 2%		–0.5			V	A
	VOCM voltage range high	VOCM gain < 2%				0.5	V	A
V_OO	Output offset voltage	All gain settings		–40		40	mV	A
	VOCM gain				1.0		V	C
V_OCM	Common-mode offset voltage	VOCM pin driven to GND		–10		10	mV	A
POWER DOWN (PD Pin)
	Power-down quiescent current			1	7	12	mA	A
	PD bias current	PD = 2.5 V			80	100	µA	A
	Turn-on time delay	Time to V_O = 90% of final value			70		ns	C
	Turn-off time delay	Time to V_O = 10% of original value			10		ns	C
DIGITAL INPUT/OUTPUT
V_IH	High-level input voltage	Referred to GND		1.2		VS+	V	A
V_IL	Low-level input voltage	Referred to GND				0.8	V	A
V_OH	High-level output voltage	1 kΩ to GND		1.4			V	A
V_OL	Low-level output voltage	1 kΩ to GND				0.4	V	A

(1) Test levels: (A) 100% DC tested at 25°C unless otherwise specified. Over-temperature limits by characterization and simulation. (B) Limits set by bench verification and simulation. (C) Typical value only for information.

(2) Ensured by design.

(3) Reference to negative edge of SCLK.

(4) Reference to positive edge of SCLK.

7.6 SPI Timing Requirements⁽²⁾

At T_A = 25°C, VS– = –2.5 V, VS+ = 2.5 V, VOCM = 0 V, R_LOAD = 200-Ω differential (R_o_{(internal, diff)} = 20 Ω), V_O = 2 V_PPD, and A_V = 26 dB, unless otherwise noted. Limits set by bench verification and simulation.

		MIN	MAX	UNIT
f_{s_c}	SCLK frequency		50	MHz
t_PH	SCLK pulse duration, high	10		ns
t_PL	SCLK pulse duration, low	10		ns
t_SU	SDI setup	3		ns
t_H	SDO hold	3		ns
t_IZ	SDO tri-state		3	ns
t_ODZ	SDO driven to tri-state⁽³⁾		5	ns
t_OZD	SDO tri-state to driven		3	ns
t_OD	SDO output delay⁽³⁾		3	ns
t_CSS	CS setup⁽⁴⁾	3		ns
t_CSH	CS hold	3		ns
t_IAG	Inter-access gap	20		ns

7.7 Typical Characteristics

At T_A = 25°C, VS– = –2.5 V, VS+ = 2.5 V, VOCM = 0 V, R_LOAD = 200-Ω differential (R_o_{(internal, diff)} = 20 Ω), V_O = 2 V_PPD, and A_V = 26 dB, unless otherwise noted. Differential input and output, and input and output pins referenced to mid-supply, unless otherwise noted. Measured using an EVM as discussed in the Parameter Measurement Information section.

Figure 1. Voltage Gain vs Frequency (1-dB Gain Steps)

Figure 3. S-Parameters vs Frequency

Figure 5. Frequency Response vs Capacitive Load

P_O = –2 dBm per tone

Figure 7. Output IP3 vs Frequency and Temperature

Figure 9. Output IP3 vs Total Output Power per Tone

Figure 11. Second-Order Harmonic Distortion vs Frequency

Figure 13. Second-Order Harmonic Distortion vs Frequency

f = 500 MHz

Figure 15. Harmonic Distortion vs Gain Settings

f = 500 MHz

Figure 17. Second-Order Harmonic Distortion vs Temperature

f = 500 MHz, (VS+) – (VS–) = 4 V

Figure 19. Second-Order Harmonic Distortion vs Temperature

f = 500 MHz

Figure 21. Harmonic Distortion vs
Output Common-Mode Voltage

Figure 23. Output P1dB vs Frequency

Figure 25. Noise Figure vs Frequency

Scc21 / Sdd21

Figure 27. CMRR vs Frequency

Figure 29. Overdrive Recovery (A_V = 26 dB)

f = 500 MHz

Figure 31. Cumulative Gain and Phase Step Error vs
Gain Settings

Figure 33. Output Impedance vs Frequency

Figure 35. Output Step Response

Figure 37. Gain Switching Response (A_V = 26 dB to 18 dB)

Figure 39. Gain Switching Response (A_V = 26 dB to 10 dB)

Figure 41. Gain Switching Response (A_V = 26 dB to 2 dB)

Figure 2. Maximum Gain vs Temperature

Figure 4. Input Return Loss vs Gain Settings

P_O = –2 dBm per tone

Figure 6. Output IP3 vs Frequency and Gain Settings

f = 500 MHz, P_O = –2 dBm per tone

Figure 8. Output IP3 vs Supply Voltage and Temperature

P_O = –2 dBm per tone

Figure 10. Intermodulation Distortion vs Frequency

Figure 12. Third-Order Harmonic Distortion vs Frequency

Figure 14. Third-Order Harmonic Distortion vs Frequency

f = 500 MHz

Figure 16. Harmonic Distortion vs Differential V_PP

f = 500 MHz

Figure 18. Third-Order Harmonic Distortion vs
Temperature

f = 500 MHz, (VS+) – (VS–) = 4 V

Figure 20. Third-Order Harmonic Distortion vs
Temperature

f = 500 MHz, gain = –6 dB

Figure 22. Harmonic Distortion vs Input CM Voltage

Figure 24. Output P1dB vs Temperature

Figure 26. Noise Figure vs Gain Settings

Sdc21/Sdd21

Figure 28. Output Balance Error vs Frequency

Figure 30. Overdrive Recovery (A_V = 10 dB)

Figure 32. Input Impedance vs Frequency

Figure 34. Supply Current vs Temperature

Figure 36. Power-Down Transition Response

Figure 38. Gain Switching Response (A_V = 18 dB to 26 dB)

Figure 40. Gain Switching Response (A_V = 10 dB to 26 dB)

Figure 42. Gain Switching Response (A_V = 2 dB to 26 dB)

封裝選項

機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 SPI Timing Requirements(2)

7.7 Typical Characteristics

7.6 SPI Timing Requirements⁽²⁾