9.4.1 Power-On Reset (POR)

The LMH6401 has a built-in, power-on reset (POR) that sets the device registers to their default state (see Table 3) on power-up. Note that the LMH6401 register information is lost each time power is removed. When power is reapplied, the POR ensures the device enters a default state. Power glitches (of sufficient duration) can also initiate the POR and return the device to a default state.

9.4.2 Power-Down (PD)

The device supports power-down control using an external power-down (PD) pin or by writing a logic high to bit 6 of SPI register 2h (see the Register Maps section). The external PD is an active high pin. When left floating, the device defaults to an on condition when the PD pin defaults to logic low as a result of the internal pulldown resistor. The device PD thresholds are noted in the Electrical Characteristics table. The device consumes approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down mode.

9.4.3 Thermal Feedback Control

The LMH6401 has a thermal feedback gain and frequency control feature that allows for improved low-frequency settling performance. The Thermal Feedback Gain Control and Thermal Feedback Frequency Control registers set through the SPI control this feature. The default setting is described in Table 3. Graphs are Included in the Application and Implementation section that illustrate how the thermal feedback gain and frequency control allows for enhanced performance.

9.4.4 Gain Control

The LMH6401 gain can be controlled from 26-dB gain (0-dB attenuation) to –6-dB gain in 1-dB steps by digitally programming the SPI register 2h. See the Register Maps section for more details.

9.5.1 Details of the Serial Interface

The LMH6401 has a set of internal registers that can be accessed by the serial interface controlled by the CS (chip select), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface readback data) pins. Serial input to the device is enabled when CS is low. SDI serial data are latched at every SCLK rising edge when CS is active (low). Serial data are loaded into the register at every 16th SCLK rising edge when CS is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active CS pulse. The first eight bits form the register address and the remaining eight bits form the register data. The interface can function with SCLK frequencies from 50 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle. A summary of the LMH6401 SPI protocol follows:

• SPI-1.1 compliant interface
• SPI register contents protected in power-down
• SPI-controlled power-down
• Powered from the main VS+ power supply
• 1.8-V logic compliant

9.5.2 Timing Diagrams

Figure 47 and Figure 48 show timing diagrams for the SPI write and read bus cycles, respectively. Figure 49 and Figure 50 show timing diagrams for the write and read operations, respectively, of the LMH6401. Figure 51 and Figure 52 illustrate example SPI stream write and read timing diagrams, respectively. Refer to the Electrical Characteristics table for SPI timing requirements.

Figure 47. SPI Write Bus Cycle

Figure 48. SPI Read Bus Cycle

Figure 49. Write Operation Timing Diagram

Figure 50. Read Operation Timing Diagram

Figure 51. SPI Streaming Write Example

Figure 52. SPI Streaming Read Example

Table 3. SPI Register Map

9.6.1 Revision ID (address = 0h, Read-Only) [default = 03h]

9.6.2 Product ID (address = 1h, Read-Only) [default = 00h]

9.6.3 Gain Control (address = 2h) [default = 20h]

9.6.4 Reserved (address = 3h) [default = 8Ch]

9.6.5 Thermal Feedback Gain Control (address = 4h) [default = 27h]

9.6.6 Thermal Feedback Frequency Control (address = 5h) [default = 45h]