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ZHCSIC8B April 2016 – June 2018 LMH0324

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

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散熱焊盤機械數據 (封裝 | 引腳)

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- QFND450A

訂購信息

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER
PD_1P8V	Power Consumption⁽³⁾	Measured with PRBS-10, VOD = Default, only OUT0 enabled, 2.97 Gbps, VIN=VDD_LDO=VDDIO=1.8 V		78		mW
PD_1P8V	Power Consumption⁽³⁾	Measured with PRBS-10, VOD = Default, OUT0 and OUT1 enabled, 2.97 Gbps, VIN=VDD_LDO=VDDIO=1.8 V		100		mW
PD_Z1P8V	Power Consumption⁽³⁾	Power Save Mode: No input signal, VIN=VDD_LDO=VDDIO=1.8 V		15		mW
PD_2P5V	Power Consumption⁽³⁾	Measured with PRBS-10, 2.97 Gbps, VOD = Default, only OUT0 enabled, VIN=VDDIO=2.5 V		128		mW
PD_2P5V	Power Consumption⁽³⁾	Measured with PRBS-10, 2.97 Gbps, VOD = Default, OUT0 and OUT1 enabled, VIN=VDDIO=2.5 V		147		mW
PD_Z2P5V	Power Consumption⁽³⁾	Power Save Mode: No input signal, VIN=VDDIO=2.5 V		28		mW
IDD	Current Consumption⁽³⁾	Measured at 1.8 V supply with PRBS-10, 2.97 Gbps, VOD = Default, only OUT0 enabled		43	55	mA
IDD	Current Consumption⁽³⁾	Measured at 2.5 V supply with PRBS-10, 2.97 Gbps, VOD = Default, only OUT0 enabled		51	71	mA
IDD_{Z_1P8V}	Current Consumption⁽³⁾	Forced Power Save Mode: MODE_SEL = LEVEL-H, Measured at 1.8 V supply, VIN=VDD_LDO=VDDIO=1.8 V		4	10	mA
V_LDO	LDO 1.8 V Output Voltage	VIN = VDDIO = 2.5 V	1.71	1.8	1.89	V
LVCMOS DC SPECIFICATIONS
V_IH	High Level Input Voltage	2-Level Input (SS_N, SCK, MOSI), VDDIO = 2.5 V or 1.8 V	0.7 x VDDIO		VDDIO + 0.3	V
V_IH	High Level Input Voltage	2-Level Input (SCL, SDA), VDDIO = 2.5 V	0.7 x VDDIO		3.6	V
V_IL	Low Level Input Voltage	2-Level Input (SS_N, SCK, MOSI) VDDIO = 2.5 V or 1.8 V	-0.3		0.3 x VDDIO	V
V_IL	Low Level Input Voltage	2-Level Input (SCL, SDA), VDDIO = 2.5 V	0		0.3 x VDDIO	V
V_OH	High Level Output Voltage	I_OH = -2 mA, (MISO), VDDIO = 2.5 V or 1.8 V	0.8 x VDDIO		VDDIO	V
V_OL	Low Level Output Voltage	I_OL = 2 mA, (MISO), VDDIO = 2.5 V or 1.8 V	0		0.2 x VDDIO	V
V_OL	Low Level Output Voltage	I_OL = 3 mA, (CD_N, SCL, SDA), VDDIO = 2.5 V	0		0.4	V
I_IH	Input High Leakage Current	SPI Mode: LVCMOS (SS_N, SCK, MOSI), Vinput = VDDIO			15	µA
I_IH	Input High Leakage Current	SMBus Mode: LVCMOS (CD_N, SCL, SDA), Vinput = VDDIO			10	µA
I_IL	Input Low Leakage Current	SPI Mode: LVCMOS (SS_N), Vinput = VSS	-40			µA
		SPI Mode: LVCMOS (SCK, MOSI), Vinput = VSS	-15
		SMBus Mode: LVCMOS (CD_N, SCL, SDA), Vinput = VSS	-10
4-LEVEL LOGIC DC SPECIFICATIONS (REFERENCE TO VDDIO, APPLY TO ALL 4-LEVEL INPUT CONTROL PINS)
V_{4_LVL_H}	LEVEL-H Input Voltage	External pull-up 1 kΩ to VDDIO		VDDIO		V
V_{4_LVL_F}	LEVEL-F Default Voltage	Float, VDDIO = 2.5 V or 1.8 V		2/3 x VDDIO		V
V_{4_LVL_R}	LEVEL-R Input Voltage	External pull-down 20 kΩ to VSS, VDDIO = 2.5 V or 1.8 V		1/3 x VDDIO		V
V_{4_LVL_L}	LEVEL-L Input Voltage	External pull-down 1 kΩ to VSS		0		V
I_{4_LVL_IH}	Input High Leakage Current	4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VDDIO	20	45	80	µA
I_{4_LVL_IH}	Input High Leakage Current	SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VDDIO	20	45	80	µA
I_{4_LVL_IL}	Input Low Leakage Current	4-Levels (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL), Vinput = VSS	-160	–93	-40	µA
I_{4_LVL_IL}	Input Low Leakage Current	SMBus Mode: 4-Levels (ADDR0, ADDR1), Vinput = VSS	-160	–93	-40	µA
RECEIVER SPECIFICATIONS (IN0+)
R_{IN0_TERM}	DC Input Termination	IN0+ and IN0- to VSS	63	75	87	Ω
RL_IN0	Input Return Loss Reference to 75 Ω⁽¹⁾	S11, 5 MHz to 1.485 GHz		–20		dB
RL_IN0	Input Return Loss Reference to 75 Ω⁽¹⁾	S11, 1.485 GHz to 3 GHz		–18		dB
V_{IN0_CM}	IN0 DC Common Mode Voltage	Input common mode voltage at IN0+ to VSS		1.4		V
V_WANDER	Input DC Wander	SD signal at IN0+, Input launch amplitude = 0.8 Vp-p		100		mVp-p
V_WANDER	Input DC Wander	HD, 3G signal at IN0+, Input launch amplitude = 0.8 Vp-p		50		mVp-p
OUTPUT DRIVERS (OUT0± OR OUT1±)
VOD	Output Differential Voltage⁽⁴⁾	8T pattern, see Figure 6, VOD_DE = LEVEL-H SD, HD, and 3G		410		mVp-p
		8T pattern, see Figure 6,VOD_DE = LEVEL-F SD, HD, and 3G	485	560	620
		8T pattern, see Figure 6, VOD_DE = LEVEL-R SD, HD, and 3G		635
		8T pattern, see Figure 6, VOD_DE = LEVEL-L SD, HD, and 3G		810
VOD_DE	De-emphasized Output Differential Voltage⁽⁴⁾	8T pattern, see Figure 7, VOD_DE = LEVEL-H SD, HD, and 3G		410
		8T pattern, see Figure 7, VOD_DE = LEVEL-F Default SD, HD, and 3G		500
		8T pattern, see Figure 7, VOD_DE = LEVEL-R SD, HD, and 3G		480
		8T pattern, see Figure 7, VOD_DE = LEVEL-L SD, HD, and 3G		480
R_{OUT_TERM}	DC Output Differential Termination	Measured across OUTn+ and OUTn-	80	100	120	Ω
t_R/t_F	Output Rise or Fall Time ⁽²⁾	20% - 80% using 8T Pattern 270 Mbps, 1.485 Gbps, 2.97 Gbps, measured after 1 inch trace		45		ps
D_R	Input Data Rate		125			Mbps Gbps
D_R	Input Data Rate				2.97	Mbps Gbps
JIT_RATE	Jitter for Various Cable Length⁽²⁾	2.97 Gbps B1694A: 0 – 150 m		0.25		UI
		2.97 Gbps B1694A: 150 m		0.25	0.4
		2.97 Gbps B1694A: 150 - 200 m		0.55
		1.485 Gbps B1694A: 0 – 200 m		0.2
		1.485 Gbps B1694A: 200 m		0.2	0.35
		1.485 Gbps B1694A: 200 – 300 m		0.55
		270 Mbps B1694A: 0 – 400 m		0.2
		270 Mbps B1694A: 400 m		0.15	0.3
		270 Mbps B1694A: 400 – 600 m		0.35
T_ADAPT	Equalizer Adapt Time - Signal detect to Adaptation Completed	PRBS-10, Belden 1694A coax cable, nominal launch amplitude of 0.8 Vpp, 2.97 Gbps		5		ms

(1) This parameter was measured with an LMH0324-18EVM.

(2) This parameter was measured with an LMH0324-18EVM.

(3) Measured with RSV_L tied to VSS.

(4) ATE production tested with DC method.