ZHCSH62B December 2017 – October 2019 LM76002-Q1 , LM76003-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed-Frequency, Peak-Current-Mode Control
- 7.3.2 Light Load Operation Modes — PFM and FPWM
- 7.3.3 Adjustable Output Voltage
- 7.3.4 Enable (EN Pin) and UVLO
- 7.3.5 Internal LDO, VCC UVLO, and Bias Input
- 7.3.6 Soft Start and Voltage Tracking (SS/TRK)
- 7.3.7 Adjustable Switching Frequency (RT) and Frequency Synchronization
- 7.3.8 Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout Conditions
- 7.3.9 Internal Compensation and CFF
- 7.3.10 Bootstrap Voltage and VBOOT UVLO (BOOT Pin)
- 7.3.11 Power Good and Overvoltage Protection (PGOOD)
- 7.3.12 Overcurrent and Short-Circuit Protection
- 7.3.13 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Custom Design With WEBENCH® Tools
- 8.2.2.2 Output Voltage Setpoint
- 8.2.2.3 Switching Frequency
- 8.2.2.4 Input Capacitors
- 8.2.2.5 Inductor Selection
- 8.2.2.6 Output Capacitor Selection
- 8.2.2.7 Feed-Forward Capacitor
- 8.2.2.8 Bootstrap Capacitors
- 8.2.2.9 VCC Capacitors
- 8.2.2.10 BIAS Capacitors
- 8.2.2.11 Soft-Start Capacitors
- 8.2.2.12 Undervoltage Lockout Setpoint
- 8.2.2.13 PGOOD
- 8.2.2.14 Synchronization
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.9 Internal Compensation and CFF
The LM76002-Q1/LM76003-Q1 is internally compensated with RC = 600 kΩ and CC = 35 pF as shown in the Functional Block Diagram. The internal compensation is designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. TI recommends placing an external feed-forward cap CFF in parallel with the top resistor divider RFBT for optimum transient performance.
Figure 19. Feed-Forward Capacitor for Loop Compensation The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by Equation 11:
An additional pole is also introduced with CFF at the frequency of Equation 12:
Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The zero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helps maintaining proper gain margin at frequency beyond the crossover.
Electrolytic capacitors have much larger ESR and the ESR zero frequency would be low enough to boost the phase up around the crossover frequency.
Designs using mostly electrolytic capacitors at the output may not need any CFF. The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It could also couple too much transient voltage deviation and falsely trip PGOOD thresholds. Therefore, calculate CFF based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced. See Feed-Forward Capacitor for the calculation of CFF.