ZHCSK76 September 2019 LM74202-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Undervoltage Lockout (UVLO)
- 8.3.2 Overvoltage Protection (OVP)
- 8.3.3 Reverse Battery Protection
- 8.3.4 Hot Plug-In and In-Rush Current Control
- 8.3.5 Overload and Short Circuit Protection
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2 Detailed Design Procedure
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
8.3.5.5 IN, OUT, RTN and GND Pins
The device has two pins for input (IN) and output (OUT). All IN pins must be connected together and to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended input operating voltage range is 4.2 V to 40 V. Similarly all OUT pins must be connected together and to the load. V(OUT), in the ON condition, is calculated using Equation 9.
where
- RON is the total ON resistance of the internal FETs.
The GND pin must be connected to the system ground. RTN is the device ground reference for all the internal control blocks. Connect the device support components: R(ILIM), C(dVdT), R(IMON), R(MODE) and resistors for UVLO and OVP with respect to the RTN pin. Internally, the device has reverse input polarity protection block between RTN and the GND terminal. Connecting RTN pin to GND pin disables the reverse input polarity protection feature. if negative input voltage is applied on IN pins with RTN pin connected to GND, the device can get damaged.