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ZHCSLU2C December 2021 – August 2024 LM63440-Q1 , LM63460-Q1

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RYF|22
- MPQF610A

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: V_IN = 13.5V. VIN1 shorted to VIN2 = V_IN. V_OUT is the converter output voltage.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE AND CURRENT
V_{IN_OPERATE}	Input operating voltage⁽¹⁾	Needed to start up	3.95			V
V_{IN_OPERATE}	Input operating voltage⁽¹⁾	Once operating	3.0			V
V_{IN_OPERATE_H}	Hysteresis⁽¹⁾			1		V
I_{Q_VIN}	Operating quiescent current (not switching)⁽²⁾	V_FB = +5%, V_BIAS = 5V, V_OUT = 5V		9	18	μA
I_Q	Operating quiescent current (not switching); measured at VIN pin⁽³⁾	V_FB = +5%, V_BIAS = 5V		0.6	6	μA
I_BIAS	Current into BIAS pin (not switching, maximum at T_J = 125°C)⁽³⁾	V_FB = +5%, V_BIAS = 5V, AUTO mode		24	31.2	μA
I_SD	Shutdown quiescent current; measured at VIN pin	V_EN = 0V, T_J= 25°C		0.6	6	μA
ENABLE
V_EN-TH	Enable input threshold voltage (rising)			1.263		V
V_EN-ACC	Enable input threshold voltage – rising deviation from typical		–5%		5%
V_EN-HYST	Enable threshold hysteresis as percentage of V_EN-TH (typical)		24%	28%	32%
V_EN-WAKE	Enable wake-up threshold		0.4			V
I_EN	Enable pin input current	V_IN = V_EN = 13.5V		2.3		nA
V_{EN_SYNC_E}	Use this edge height to sync using EN/SYNC pin	Rise/fall time < 30ns	2.4			V
LDO AND VCC
V_CC	Internal V_CC voltage	V_BIAS > 3.4V, CCM operation⁽¹⁾		3.3		V
V_CC	Internal V_CC voltage	V_BIAS = 3.1V, non-switching		3.1		V
V_CC-UVLO	Internal V_CC undervoltage lockout	V_CC rising undervoltage threshold		3.6		V
V_CC-UVLO-HYST	Internal V_CC undervoltage lockout hysteresis	Hysteresis below V_CC-UVLO		1.1		V
FEEDBACK
V_{FB_acc}	Initial reference voltage accuracy	V_IN = 3.3V to 36V, T_J = 25°C, FPWM mode	–1%		1%
I_FB	Input current from FB to GND	Adjustable versions only, V_FB = 1V		1	50	nA
OSCILLATOR
f_ADJ	Minimum adjustable frequency by RT pin	R_RT = 66.5k?	0.18	0.2	0.22	MHz
	Adjustable frequency by RT pin with 400kHz setting	R_RT = 33.2k?	0.36	0.4	0.44	MHz
	Maximum adjustable frequency by RT pin	R_RT = 5.76k?	1.98	2.2	2.42	MHz
f_{S_SS}	Frequency span of spread spectrum operation – largest deviation from center frequency	Spread spectrum active		2%
f_PSS	Spread spectrum pattern frequency⁽¹⁾	Spread spectrum active, f_SW = 2.1MHz			1.5	Hz
MOSFETS
R_DS(on)HS	Power switch on-resistance	High-side MOSFET R_DS(on)		41	82	m?
R_DS(on)LS	Power switch on-resistance	Low-side MOSFET R_DS(on)		21	45	m?
V_BOOT-UVLO	Voltage on CBOOT relative to SW that turns off the high-side switch			2.1		V
CURRENT LIMITS
I_L-HS	High-side switch current limit, LM63460-Q1⁽⁴⁾	Duty cycle approaches 0%	8.9	10.3	11.5	A
I_L-HS	High-side switch current limit, LM63440-Q1⁽⁴⁾	Duty cycle approaches 0%	6	7	8.1	A
I_L-LS	Low-side switch current limit, LM63460-Q1		6.1	7.1	8.1	A
I_L-LS	Low-side switch current limit, LM63440-Q1		4.0	4.8	5.4	A
I_L-ZC	Zero-cross current limit. Positive current direction is out of the SW pin	AUTO mode, static measurement		0.25		A
I_L-NEG	Negative current limit. Positive current direction is out of the SW pin, LM63460-Q1	FPWM operation		–3		A
I_L-NEG	Negative current limit FPWM and SYNC Modes. Positive current direction is out of the SW pin, LM63440-Q1	FPWM operation		–2		A
I_{PK_MIN_0}	Minimum peak command in AUTO mode / device current rating	Pulse duration < 100ns		25%
I_{PK_MIN_100}	Minimum peak command in AUTO mode / device current rating	Pulse duration > 1μs		12.5%
V_HICCUP	Ratio of FB voltage to in-regulation FB voltage	Hiccup disabled during soft start		40%
POWER GOOD
PGD_OV	PGOOD upper threshold – rising	% of V_OUTsetting	105%	107%	110%
PGD_UV	PGOOD lower threshold – falling	% of V_OUTsetting	92%	94%	96.5%
PGD_HYST	PGOOD hysteresis	% of V_OUTsetting		1.3%
V_{IN(PGD-VALID)}	Input voltage for proper PGOOD function		1.0			V
V_PGD(LOW)	Low-level PGOOD function output voltage	46μA pullup to PGOOD, V_IN = 1V, V_EN = 0V			0.4	V
		1mA pullup to PGOOD, V_EN = 0V			0.4
		2mA pullup to PGOOD, V_EN = 3.3V			0.4
R_PGD	R_DS(on) of PGOOD output	1mA pullup to PGOOD, V_EN = 0V		17	40	?
R_PGD	R_DS(on) of PGOOD output	1mA pullup to PGOOD, V_EN = 3.3V		40	90	?
I_OV	Pulldown current at the SW node in an overvoltage condition			0.5		mA
THERMAL SHUTDOWN
T_SHD	Thermal shutdown rising threshold⁽¹⁾		158	168	180	℃
T_SHD-HYS	Thermal shutdown hysteresis⁽¹⁾			10		℃

(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.

(2) I_{Q_VIN} = I_Q + I_BIAS × (V_OUT / V_IN)

(3) This is the current used by the device while not switching, open loop, with FB pulled to +5% above nominal. It does not represent the total input current to the converter while regulating.

(4) High-side current limit is a function of duty cycle. High-side current limit value is highest at small duty cycle and less at higher duty cycle.