ZHCSLU2C December 2021 – August 2024 LM63440-Q1 , LM63460-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Input Voltage Range (VIN1, VIN2)
- 7.3.2 Output Voltage Setpoint (FB)
- 7.3.3 Precision Enable and Input Voltage UVLO (EN/SYNC)
- 7.3.4 Frequency Synchronization (EN/SYNC)
- 7.3.5 Clock Locking
- 7.3.6 Adjustable Switching Frequency (RT)
- 7.3.7 Power-Good Monitor (PGOOD)
- 7.3.8 Bias Supply Regulator (VCC, BIAS)
- 7.3.9 Bootstrap Voltage and UVLO (CBOOT)
- 7.3.10 Spread Spectrum
- 7.3.11 Soft Start and Recovery From Dropout
- 7.3.12 Overcurrent and Short-Circuit Protection
- 7.3.13 Thermal Shutdown
- 7.3.14 Input Supply Current
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1 Design 1 – Automotive Synchronous 6A Buck Regulator at 2.1MHz
- 8.2.2
Design 2 – Automotive Synchronous 4A Buck Regulator at 2.1MHz
- 8.2.2.1 Design Requirements
- 8.2.2.2
Detailed Design Procedure
- 8.2.2.2.1 Custom Design With WEBENCH? Tools
- 8.2.2.2.2 Setting the Output Voltage
- 8.2.2.2.3 Choosing the Switching Frequency
- 8.2.2.2.4 Inductor Selection
- 8.2.2.2.5 Output Capacitor Selection
- 8.2.2.2.6 Input Capacitor Selection
- 8.2.2.2.7 Bootstrap Capacitor
- 8.2.2.2.8 VCC Capacitor
- 8.2.2.2.9 BIAS Power Connection
- 8.2.2.2.10 Feedforward Network
- 8.2.2.2.11 Input Voltage UVLO
- 8.2.2.3 Application Curves
- 8.2.3 Design 3 – Automotive Synchronous 6A Buck Regulator at 400kHz
- 8.3 Power Supply Recommendations
- 8.4 Layout
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.3.4 Frequency Synchronization (EN/SYNC)
Use the EN/SYNC pin of the LM634X0-Q1 to synchronize the internal oscillator to an external clock signal ranging from 200kHz to 2.2MHz. The internal oscillator can be synchronized by AC coupling a positive clock edge to EN/SYNC, as shown in Figure 7-1.
TI recommends to keep the parallel combination value of RENT and RENB in the 100kΩ range. RENT is required for synchronization, but RENB can be left unmounted. The external clock must be off before start-up to allow proper start-up sequencing.
Referring to Figure 7-2, the AC-coupled voltage edge at EN/SYNC must exceed the SYNC amplitude threshold, VEN_SYNC, to trip the internal synchronization pulse detector. In addition, the minimum EN/SYNC rising pulse and falling pulse durations must be longer than tSYNC_EDGE and shorter than the blanking time, tB. A 3.3V or higher amplitude pulse signal coupled through a 1nF capacitor, CSYNC, is suggested.
Figure 7-2 Typical Synchronization
Waveform Applied to EN/SYNCAfter a valid synchronization signal is applied for 2048 cycles, the clock frequency quickly changes to that of the applied signal. Synchronization overrides spread spectrum, turning it off.