ZHCSLD0B May 2020 – June 2021 LM62435-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE AND CURRENT | ||||||
| VIN_OPERATE | Input operating voltage(2) | Needed to start up | 3.95 | V | ||
| Once operating | 3.0 | |||||
| VIN_OPERATE_H | Hysteresis(2) | 1 | V | |||
| IQ_VIN | Operating quiescent current (not switching)(3) | VFB = +5%, VBIAS = 5 V | 9 | 18 | μA | |
| ISD | Shutdown quiescent current; measured at VIN pin | EN = 0 V, TJ = 25℃ | 0.6 | 6 | μA | |
| ENABLE | ||||||
| VEN | Enable input threshold voltage - rising | 1.263 | V | |||
| VEN-ACC | Enable input threshold voltage - rising deviation from typical | -5 | 5 | % | ||
| VEN-HYST | Enable threshold hysteresis as percentage of VEN (TYP) | 24 | 28 | 32 | % | |
| VEN-WAKE | Enable wake-up threshold | 0.4 | V | |||
| IEN | Enable pin input current | VIN = EN = 13.5 V | 2.3 | nA | ||
| LDO - VCC | ||||||
| VCC | Internal VCC voltage | VBIAS > 3.4 V, CCM Operation(2) | 3.3 | V | ||
| VBIAS = 3.1 V, Non-switching | 3.1 | |||||
| VCC_UVLO | Internal VCC input under voltage lock-out | VCC rising under voltage threshold | 3.6 | V | ||
| VCC_UVLO_HYST | Internal VCC input under voltage lock-out | Hysteresis below VCC_UVLO | 1.1 | V | ||
| FEEDBACK | ||||||
| VFB_acc | Initial reference voltage accuracy | VIN = 3.3 V to 36 V, FPWM Mode | -1 | 1 | % | |
| VOUT_acc | Reference voltage accuracy for Fixed 3.3-V VOUT trim option | VIN = 13.5 V, FPWM Mode | 3.2587 | 3.3 | 3.3413 | V |
| VOUT_acc | Reference voltage accuracy for Fixed 5-V VOUT trim option | VIN = 13.5 V, FPWM Mode | 4.9375 | 5 | 5.0625 | V |
| RFB | Resistance from FB to AGND | 5-V Option | 1.85 | M? | ||
| 3.3-V Option | 2.1 | |||||
| IFB | Input current from FB to AGND | Adjustable versions only, FB = 1 V | 10 | nA | ||
| OSCILLATOR | ||||||
| fADJ | Minimum adjustable frequency by SYNC | 0.18 | 0.2 | 0.22 | MHz | |
| Adjustable frequency by SYNC | 0.36 | 0.4 | 0.44 | MHz | ||
| Maximum adjustable frequency by SYNC | 1.98 | 2.2 | 2.42 | MHz | ||
| fSW | Switching frequency | VIN = 13.5 V, Center frequency with or without spread spectrum, PWM operation | 1.9 | 2.1 | 2.3 | MHz |
| fS SS | Frequency span of spread spectrum operation - largest deviation from center frequency | Spread spectrum active | 2 | % | ||
| fPSS | Spread spectrum pattern frequency(2) | Spread spectrum active, fSW = 2.1 MHz | 1.5 | Hz | ||
| MODE/SYNC PIN | ||||||
| IMODE/SYNC | MODE/SYNC pin leakage current after startup | VIN = 13.5 V, VSYNC/MODE = 3.3 V | 1 | nA | ||
| VIN = 13.5 V, VSYNC/MODE = 5.5 V | 1 | |||||
| VMODE_L | MODE/SYNC input voltage low | 0.4 | V | |||
| VMODE_H | MODE/SYNC input voltage high | 1.6 | V | |||
| VSYNCD_HYST | MODE/SYNC input voltage hysteresis | 0.155 | 1 | V | ||
| VMODE_H2 | Spread spectrum on if MODE/SYNC voltage is below this voltage and above VMODE_H | Level dependent operation | 2.5 | V | ||
| VMODE_H3 | Spread spectrum off if MODE/SYNC is above this voltage | Level dependent operation | 4.9 | V | ||
| RMODE_H | MODE/SYNC attached resistance indicating Spread Spectrum off | Level dependent operation | 30 | k? | ||
| RMODE_L | MODE/SYNC attached resistance indicating Spread Spectrum on | Level dependent operation | 6 | k? | ||
| MOSFETS | ||||||
| RDS(ON)_HS | Power switch on-resistance | High side MOSFET RDS(ON) | 41 | 82 | m? | |
| RDS(ON)_LS | Power switch on-resistance | Low side MOSFET RDS(ON) | 21 | 45 | m? | |
| VBOOT_UVLO | Voltage on CBOOT pin compared to SW which will turn off high-side switch | 2.1 | V | |||
| CURRENT LIMITS | ||||||
| IL-HS | High side switch current limit(1) | Duty cycle approaches 0% | 6 | 7 | 8.1 | A |
| IL-LS | Low side switch current limit | 3.7 | 4.8 | 5.4 | A | |
| IL-ZC | Zero-cross current limit. Positive current direction is out of SW pin | Auto Mode, static measurement | 0.25 | A | ||
| IL-NEG | Negative current limit FPWM and SYNC Modes. Positive current direction is out of SW pin. | FPWM operation | -2 | A | ||
| IPK_MIN_0 | Minimum peak command in Auto Mode / device current rating | Pulse duration < 100 ns | 25 | % | ||
| IPK_MIN_100 | Minimum peak command in Auto Mode / device current rating | Pulse duration > 1 μs | 12.5 | % | ||
| VHICCUP | Ratio of FB voltage to in-regulation FB voltage | Not during soft start | 40 | % | ||
| POWER GOOD | ||||||
| PGDOV | PGOOD upper threshold - rising | % of VOUT setting | 105 | 107 | 110 | % |
| PGDU V | PGOOD lower threshold - falling | % of VOUT setting | 92 | 94 | 96.5 | % |
| PGDHYST | PGOOD upper threshold (rising & falling) | % of VOUT setting | 1.3 | % | ||
| VIN(PGD_VALID) | Input voltage for proper PGOOD function | 1.0 | V | |||
| VPGD(LOW) | Low level PGOOD function output voltage | 46 μA pullup to PGOOD pin, VIN = 1.0 V, EN = 0 V | 0.4 | V | ||
| 1 mA pullup to PGOOD pin, VIN = 13.5 V, EN = 0 V | 0.4 | |||||
| 2 mA pullup to PGOOD pin, VIN = 13.5 V, EN = 3.3 V | 0.4 | |||||
| RPGD | RDS(ON) of PGOOD output | 1 mA pullup to PGOOD pin, EN = 0 V | 17 | 40 | ? | |
| 1 mA pullup to PGOOD, EN = 3.3 V | 40 | 90 | ? | |||
| IOV | Pull down current at the SW node under over voltage condition | 0.5 | mA | |||
| THERMAL SHUTDOWN | ||||||
| TSD_R | Thermal shutdown rising threshold(2) | 158 | 168 | 180 | ℃ | |
| TSD_HYST | Thermal shutdown hysteresis(2) | 10 | ℃ | |||