ZHCSKZ8B March 2020 – June 2021 LM61435-Q1
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| Parameter | Test Condition | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SWITCH NODE | ||||||
| tON_MIN | Minimum HS switch on time | VIN = 20 V, IOUT = 2 A, RBOOT short to CBOOT | 55 | 70 | ns | |
| tON_MAX | Maximum HS switch on time | 9 | μs | |||
| tOFF_MIN | Minimum LS switch on time | VIN = 4.0 V, IOUT = 1 A, RBOOT short to CBOOT | 65 | 85 | ns | |
| tSS | Time from first SW pulse to VREF at 90% | VIN ≥ 4.2 V | 3.5 | 5 | 7 | ms |
| tSS2 | Time from first SW pulse to release of FPWM lockout if output not in regulation | VIN ≥ 4.2 V | 9.5 | 13 | 17 | ms |
| tW | Short circuit wait time ("Hiccup" time) | 80 | ms | |||
| ENABLE | ||||||
| tEN | Turn-on delay(1) | CVCC = 1 μF, time from EN high to first SW pulse if output starts at 0 V | 0.7 | ms | ||
| tB | Blanking of EN after rising or falling edges(1) | 4 | 28 | μs | ||
| tSYNC_EDGE | Enable sync signal hold time after edge for edge recognition | 100 | ns | |||
| POWER GOOD | ||||||
| tPGDFLT(rise) | Delay time to PGOOD high signal | 1.5 | 2 | 2.5 | ms | |
| tPGDFLT(fall) | Glitch filter time constant for PGOOD function | 120 | μs | |||