ZHCSKZ8B March 2020 – June 2021 LM61435-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 EN/SYNC Uses for Enable and VIN UVLO
- 8.3.2 EN/SYNC Pin Uses for Synchronization
- 8.3.3 Clock Locking
- 8.3.4 Adjustable Switching Frequency
- 8.3.5 PGOOD Output Operation
- 8.3.6 Internal LDO, VCC UVLO, and BIAS Input
- 8.3.7 Bootstrap Voltage and VCBOOT-UVLO (CBOOT Pin)
- 8.3.8 Adjustable SW Node Slew Rate
- 8.3.9 Spread Spectrum
- 8.3.10 Soft Start and Recovery From Dropout
- 8.3.11 Output Voltage Setting
- 8.3.12 Overcurrent and Short Circuit Protection
- 8.3.13 Thermal Shutdown
- 8.3.14 Input Supply Current
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.3.3 FPWM Mode - Light Load Operation
Like auto mode operation, FPWM mode operation during light load operation is selected as a factory option.
In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see Section 7.5 for reverse current limit values.
In FPWM mode, Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple.
Figure 8-17 FPWM Mode OperationFor all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output being pulled up.