ZHCSO42B December 2015 – July 2021 LM53625-Q1 , LM53635-Q1
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VFB | Initial output voltage accuracy | VIN = 3.8 V to 36 V, TJ = 25°C | –1% | 1% | ||
| VIN = 3.8 V to 36 V | –1.5% | 1.5% | ||||
| IQ | Operating quiescent current; measured at VIN pin when enabled and not switching(1) | VIN = 13.5 V, VBIAS = 5 V | 6 | μA | ||
| VIN = 13.5 V, VBIAS = 5 V, TJ = 85°C | 16 | |||||
| IB | Bias current into BIAS pin, enabled, not switching | VIN = 13.5 V, VBIAS = 5 V, FPWM = 0 V | 35 | μA | ||
| VIN = 13.5 V, VBIAS = 3.3 V, FPWM = 0 V | 35 | |||||
| ISD | Shutdown quiescent current; measured at VIN pin | EN ≤ 0.4 V, TJ = 25°C | 2 | μA | ||
| EN ≤ 0.4 V, TJ = 85°C | 3 | |||||
| EN ≤ 0.4V, TJ = 150°C | 5 | |||||
| VIN-OPERATE | Minimum input voltage to operate | Rising | 3.2 | 3.55 | 3.95 | V |
| Falling | 2.95 | 3.25 | 3.55 | |||
| Hysteresis | 0.28 | 0.3 | 0.4 | |||
| VRESET | RESET upper threshold voltage | Rising, % of VOUT | 105% | 107% | 110% | |
| RESET lower threshold voltage | Falling, % VOUT | 92% | 94% | 96.5% | ||
| Magnitude of RESET lower threshold from steady state output voltage | Steady-state output voltage and RESET threshold read at the same TJ and VIN | 96% | ||||
| VRESET_HYST | RESET hysteresis as a percent of output voltage setpoint | ±1 | ||||
| VRESET_VALID | Minimum input voltage for proper RESET function | 50-μA pullup to RESET pin, EN = 0 V, TJ= 25°C | 1.5 | V | ||
| VOL | Low level RESET function output voltage | 50-μA pullup to RESET pin, VIN =1.5 V, EN = 0 V | 0.4 | V | ||
| 0.5-mA pullup to RESET pin, VIN =13.5 V, EN=0 V | 0.4 | |||||
| 1-mA pullup to RESET pin, VIN =13.5 V, EN=3.3 V | 0.4 | |||||
| FSW | Switching frequency | VIN = 13.5 V, center frequency with spread spectrum, PWM operation | 1.85 | 2.1 | 2.35 | MHz |
| VIN = 13.5 V, without spread spectrum, PWM operation | 1.85 | 2.1 | 2.35 | |||
| FSYNC | Sync frequency range | 1.9 | 2.1 | 2.3 | MHz | |
| DSYNC | Sync input duty cycle range | High state input < 5.5 V and > 2.3 V | 25% | 75% | ||
| VFPWM | FPWM input threshold voltage | FPWM input high (MODE = FPWM) | 1.5 | V | ||
| FPWM input low (MODE = AUTO with diode emulation) | 0.4 | |||||
| FPWM input hysteresis | 0.15 | 1 | ||||
| FSSS | Frequency span of spread spectrum operation | ±3% | ||||
| FPSS | Spread-spectrum pattern frequency(2) | 9 | Hz | |||
| FSW-SS | Switching Frequency while in spread spectrum | VIN = 13.5 V, PWM operation | 1.81 | MHz | ||
| IFPWM | FPWM leakage current | VIN = 13.5 V, VFPWM = 3.3 V | 1 | μA | ||
| VIN = VFPWM = 13.5 V | 5 | |||||
| ISYNC | SYNC leakage current | VIN = 13.5 V, VSYNC = 3.3 V | 1 | μA | ||
| VIN = VSYNC = 13.5 V | 5 | |||||
| IL-HS | High-side switch current limit | LM53625 | 3.5 | 5 | 6.5 | A |
| LM53635 | 4.5 | 6 | 7.5 | |||
| IL-LS | Low-side switch current limit | LM53625 | 2.5 | 3.5 | 4.1 | A |
| LM53635 | 3.5 | 4.5 | 5.1 | |||
| IL-ZC | Zero-cross current limit FPWM = low | –0.02 | A | |||
| IL-NEG | Negative current limit FPWM = high | –1.5 | ||||
| RDSON | Power switch on-resistance | High-side MOSFET RDSON, VIN = 13 V, IL=1A | 60 | 130 | mΩ | |
| Low-side MOSFET RDSON, VIN = 13 V, IL=1A | 40 | 80 | ||||
| VEN | Enable input threshold voltage - rising | Enable rising | 1.7 | 2 | V | |
| VEN_HYST | Enable threshold hysteresis | 0.45 | 0.55 | V | ||
| VEN_WAKE | Enable wake-up threshold | 0.4 | V | |||
| IEN | EN pin input current | VIN = VEN = 13.5 V | 2 | 5 | μA | |
| VCC | Internal VCC voltage | VIN 13.5 V, VBIAS = 0 V | 3.05 | V | ||
| VIN = 13.5 V, VBIAS = 3.3 V | 3.15 | |||||
| VCC_UVLO | Internal VCC input undervoltage lockout | VIN rising | 2.7 | V | ||
| Hysteresis below VCC-UVLO | 185 | mV | ||||
| IFB | Input current from FB to AGND | Adjustable LM53625/35-Q1, FB=1 V | 20 | nA | ||
| VREF | Reference voltage for adjustable option only | TJ = 25°C | 0.993 | 1 | 1.007 | V |
| TJ = –40°C to 125°C | 0.99 | 1 | 1.01 | |||
| TJ = –40°C to 150°C | 0.985 | 1 | 1.015 | |||
| RRESET | RDSON of RESEToutput | Pull FB pin low. Sink 1-mA at RESET pin | 50 | 85 | Ω | |
| VSYNC | VIH | 1.5 | V | |||
| VIL | 0.4 | |||||
| VHYST | 0.15 | 1 | ||||
| TSD | Thermal shutdown thresholds(2) | Rising | 155 | 175 | °C | |
| Hysteresis | 15 | |||||
| DMAX | Maximum switch duty cycle | Fsw = 2.1 MHz | 80% | |||
| While in dropout(2) | 98% | |||||