ZHCSFE2A August 2016 – November 2017 LM5161-Q1
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Control Circuit
- 7.3.2 VCC Regulator
- 7.3.3 Regulation Comparator
- 7.3.4 Soft-Start
- 7.3.5 Error Transconductance (GM) Amplifier
- 7.3.6 On-Time Generator
- 7.3.7 Current Limit
- 7.3.8 N-Channel Buck Switch and Driver
- 7.3.9 Synchronous Rectifier
- 7.3.10 Enable / Undervoltage Lockout (EN/UVLO)
- 7.3.11 Thermal Protection
- 7.3.12 Ripple Configuration
- 7.4 Device Functional Modes
-
8 Applications and Implementation
- 8.1 Application Information
- 8.2
Typical Applications
- 8.2.1
LM5161-Q1 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load)
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Custom Design With WEBENCH® Tools
- 8.2.1.2.2 Output Resistor Divider Selection
- 8.2.1.2.3 Frequency Selection
- 8.2.1.2.4 Inductor Selection
- 8.2.1.2.5 Output Capacitor Selection
- 8.2.1.2.6 Series Ripple Resistor - RESR (FPWM = 1)
- 8.2.1.2.7 VCC and Bootstrap Capacitor
- 8.2.1.2.8 Input Capacitor Selection
- 8.2.1.2.9 Soft-Start Capacitor Selection
- 8.2.1.2.10 EN/UVLO Resistor Selection
- 8.2.1.3 Application Curves
- 8.2.2 LM5161-Q1 Isolated Fly-Buck (36-V to 72-V Input, 12-V, 12-W Isolated Output)
- 8.2.1
LM5161-Q1 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load)
- 8.3 Do's and Don'ts
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|14
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|14
訂購信息
8.2.2.2.4 Output Capacitor (CVISO)
The Fly-Buck output capacitor conducts higher ripple current than a buck converter output capacitor. The ripple voltage across the isolated output capacitor is calculated based on the time the rectifier diode is off. During this time the entire output current is supplied by the output capacitor. The required capacitance for the worst-case ripple voltage can be calculated using Equation 24 where, ΔVISO is the expected ripple voltage at the secondary output.
Equation 24 is an approximation and ignores the ripple components associated with ESR and ESL of the output capacitor. For a ΔVISO = 100 mV, Equation 24 requires CVISO = 11.12 µF. When selecting the CVISO output capacitors (C2 and C3 in the Figure 34), the DC bias must be considered in order to ensure sufficient capacitance over the output voltage.