Active EMI layout is critical for
enhanced EMI performance. Layout considerations are as follows:
- Connect AVSS to a quiet GND
connection, further from IC if possible. Keep decoupling capacitor
CAEFVDDA close to the AEFVDDA pin and AVSS GND connection. See
capacitor C23 in GUID-0999CD56-B605-4F84-9FBF-3412E0CC09AD.html#SNVSB291583.
- Route the SEN and INJ traces
differentially as close together as possible on an internal quiet layer. Avoid
noisy layer or layers carrying high-voltage traces.
- Place the active EMI
compensation components CAEFC, RAEFC, and
RAEFDC close together and near the VIN-EMI node to the
input filter inductor.
- CSEN and
CINJ components must be placed directly outside of the
compensation loop.
- Place input compensation
components RAEFC and CAEFC nearby the other Active EMI
components. Ensure the GND connection is far away from any noise sources. Do not
connect the input compensation GND near the power stage.
- Route REFAGND directly to the GND
of the input power connector. Do not tie to the GND plane connection. The
REFAGND trace can partially shield the SEN and INJ differential pair on the way
to the input power connector.