ZHCSIN4B August 2018 – June 2021 LM5146-Q1
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
A high power density, high-efficiency regulator solution uses automotive grade 100-V power MOSFETs in SON 5-mm × 6-mm packages, together with a low-DCR inductor and all-ceramic capacitor design. The design occupies a footprint of 30 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is set at 12 A based on the resistor RILIM and the 10-mΩ RDS(on) of the low-side MOSFET (typical at TJ = 25°C and VGS = 10 V). The 12-V output is connected to VCC through a diode, D1, to reduce IC bias power dissipation at high input voltages.
The selected buck converter powertrain components are cited in Table 9-8, including power MOSFETs, buck inductor, input and output capacitors, and ICs. Using the LM5146-Q1 Quickstart Calculator, compensation components are selected based on a target loop crossover frequency of 40 kHz and phase margin greater than 55°. The output voltage soft-start time is 6 ms based on the selected soft-start capacitance, CSS, of 47 nF.
| REFERENCE DESIGNATOR | QTY | SPECIFICATION | MANUFACTURER | PART NUMBER |
|---|---|---|---|---|
| CIN | 5 | 2.2 μF, 100 V, X7R, 1210, ceramic, AEC-Q200 | TDK | CGA6N3X7R2A225K |
| Taiyo Yuden | HMK325B7225KM-P | |||
| 2.2 μF, 100 V, X7S, 1206, ceramic, AEC-Q200 | Murata | GCM31CC72A225KE02 | ||
| COUT | 5 | 22 μF, 25 V, X7R, 1210, ceramic, AEC-Q200 | TDK | CGA6P3X7R1E226M |
| Murata | GCM32EC71E226KE36 | |||
| Taiyo Yuden | TMK325B7226KMHT | |||
| LF | 1 | 6.8 μH, 12 mΩ, 13.3 A, 10.85 × 10.0 × 5.2 mm, AEC-Q200 | Cyntec | VCHA105D-6R8MS6 |
| 6.8 μH, 13.3 mΩ, 21.4 A, 10.5 × 10.0 × 6.5 mm, AEC-Q200 | TDK | SPM10065VT-6R8M-D | ||
| Q1 | 1 | 100 V, 22 mΩ, MOSFET, SON 5 × 6, AEC-Q101 | Onsemi | NVMFS6B25NLT1G |
| Q2 | 1 | 100 V, 10 mΩ, MOSFET, SON 5 × 6, AEC-Q101 | Onsemi | NVMFS6B14NLT1G |
| U1 | 1 | Wide VIN synchronous buck controller, AEC-Q100 | Texas Instruments | LM5146QRGYRQ1 |
As shown in Figure 9-16, a 2.2-Ω resistor in series with CBST is used to slow the turn-on transition of the high-side MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics for more detail.