6 Pin Configuration and Functions

Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Figure 6-1 20-Pin VQFN With Wettable Flanks in RGY Package(Top View)

Table 6-1 Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NO.	NAME	I/O⁽¹⁾	DESCRIPTION
1	EN/UVLO	I	Enable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the controller is in shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V and less than 1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK voltage can ramp and pulse-width modulated gate-drive signals are delivered to the HO and LO pins. A 10-μA current source is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO resistor divider to provide hysteresis. Hysteresis can be adjusted by varying the resistance of the external divider.
2	RT	I	Oscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and the AGND. TI recommends a maximum oscillator frequency of 1 MHz. An RT pin resistor is required even when using the SYNCIN pin to synchronize to an external clock.
3	SS/TRK	I	Soft start and voltage-tracking pin. An external capacitor and an internal 10-μA current source set the ramp rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V, the amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby and fault conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB falls due to a load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery when the fault is removed. Voltage tracking can be implemented by connecting a low impedance reference between 0 V and 0.8 V to the SS/TRK pin. The 10-μA SS/TRK charging current flows into the reference and produces a voltage error if the impedance is not low. Connect a minimum capacitance from SS/TRK to AGND of 2.2 nF.
4	COMP	O	Low impedance output of the internal error amplifier. Connect the loop compensation network between the COMP pin and the FB pin.
5	FB	I	Feedback connection to the inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V.
6	AGND	P	Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.
7	SYNCOUT	O	Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-side FET gate drive. Connect SYNCOUT of the master LM5146-Q1 to the SYNCIN pin of a second LM5146-Q1 to operate two controllers at the same frequency with 180° interleaved high-side FET switch turn-on transitions. Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating from an external clock that is different from the free-running frequency set by the RT resistor.
8	SYNCIN	I	Dual function pin to provide an optional clock input and enable diode emulation by the low-side MOSFET. Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode emulation by the low-side MOSFET is disabled when the controller is synchronized to an external clock, and negative inductor current can flow in the low-side MOSFET with light loads. A continuous logic low state at the SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode emulation results in discontinuous mode operation (DCM) at light loads, which improves efficiency. A logic high state at the SYNCIN pin disables diode emulation, producing forced-PWM (FPWM) operation. During soft start when SYNCIN is high or a clock signal is present, the LM5146-Q1 operates in diode emulation mode until the output is in regulation, then gradually increases the SW zero-cross threshold, resulting in a gradual transition from DCM to FPWM.
9	NC	—	No electrical connection
10	PGOOD	O	Power-good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin is within a specified tolerance window centered at 0.8 V.
11	ILIM	I	Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an external resistor programs the threshold voltage for valley current limiting. The opposite end of the threshold adjust resistor can be connected to either the drain of the low-side MOSFET for R_DS(on) sensing or to a current sense resistor connected to the source of the low-side FET.
12	PGND	P	Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-side MOSFET or the ground side of a shunt resistor.
13	LO	P	Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through a short, low inductance path.
14	VCC	O	Output of the 7.5-V bias regulator. Locally decouple to PGND using a low-ESR/ESL capacitor located as close as possible to the controller. Controller bias can be supplied from an external supply that is greater than the internal VCC regulation voltage. Use caution when applying external bias to ensure that the applied voltage is not greater than the minimum V_IN voltage and does not exceed the VCC pin maximum operating rating. See the Recommended Operating Conditions.
15	EP	—	Pin is internally connected to exposed pad of the package. Electrically isloated.
16	NC	—	No electrical connection
17	BST	O	Bootstrap supply for the high-side gate driver. Connect to the bootstrap (boot) capacitor. The bootstrap capacitor supplies current to the high-side FET gate and must be placed as close as possible to controller. If an external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the cathode of the diode to the BST pin and anode to VCC.
18	HO	P	High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low inductance path.
19	SW	P	Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET using short, low inductance paths.
20	VIN	P	Supply voltage input for the VCC LDO regulator
—	EP	—	Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal resistance.

(1) P = Power, G = Ground, I = Input, O = Output