ZHCSLJ6A June 2021 – June 2021 LM5145-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY | ||||||
| VIN | Operating input voltage range | IVCC ≤ 10 mA at VVIN = 5.5 V | 5.5 | 75 | V | |
| IQ-RUN | Operating input current, not switching | VEN/UVLO = 1.5 V, VSS/TRK = 0 V | 1.8 | 2.1 | mA | |
| IQ-STBY | Standby input current | VEN/UVLO = 1 V | 1.75 | 2 | mA | |
| IQ-SHDN | Shutdown input current | VEN/UVLO = 0 V, VVCC < 1 V | 13.5 | 30 | μA | |
| VCC REGULATOR | ||||||
| VVCC | VCC regulation voltage | VSS/TRK = 0 V, 9 V ≤ VVIN ≤ 100 V, 0 mA ≤ IVCC ≤ 20 mA | 7.3 | 7.5 | 7.7 | V |
| VVCC-LDO | VIN to VCC dropout voltage | VVIN = 6 V, VSS/TRK = 0 V, IVCC = 20 mA | 0.25 | 0.72 | V | |
| ISC-LDO | VCC short-circuit current | VSS/TRK = 0 V, VVCC = 0 V | 40 | 50 | 70 | mA |
| VVCC-UV | VCC undervoltage threshold | VVCC rising | 4.8 | 4.93 | 5.2 | V |
| VVCC-UVH | VCC undervoltage hysteresis | Rising threshold – falling threshold | 0.26 | V | ||
| VVCC-EXT | Minimum external bias voltage | Voltage required to disable VCC regulator | 8 | V | ||
| IVCC | External VCC input current, not switching | VSS/TRK = 0 V, VVCC = 13 V | 2.3 | mA | ||
| ENABLE AND INPUT UVLO | ||||||
| VSHDN | Shutdown to standby threshold | VEN/UVLO rising | 0.42 | V | ||
| VSHDN-HYS | Shutdown threshold hysteresis | EN/UVLO Rising threshold – falling threshold | 50 | mV | ||
| VEN | Standby to operating threshold | VEN/UVLO rising | 1.164 | 1.2 | 1.236 | V |
| IEN-HYS | Standby to operating hysteresis current | VEN/UVLO = 1.5 V | 9 | 10 | 11 | μA |
| ERROR AMPLIFIER | ||||||
| VREF | FB reference Voltage | FB connected to COMP | 792 | 800 | 808 | mV |
| IFB-BIAS1 | FB input bias current | VFB = 0.8 V, –40°C ≤ TJ ≤ 125°C | –0.1 | 0.1 | μA | |
| IFB-BIAS2 | FB input bias current | VFB = 0.8 V, –40℃ ≤ TJ ≤ 150℃ | –0.2 | 0.2 | μA | |
| VCOMP-OH | COMP output high voltage | VFB = 0 V, COMP sourcing 1 mA | 5 | V | ||
| VCOMP-OL | COMP output low voltage | COMP sinking 1 mA | 0.3 | V | ||
| AVOL | DC gain | 94 | dB | |||
| GBW | Unity gain bandwidth | 6.5 | MHz | |||
| SOFT-START and VOLTAGE TRACKING | ||||||
| ISS | SS/TRK capacitor charging current | VSS/TRK = 0 V | 8.5 | 10 | 12 | μA |
| RSS | SS/TRK discharge FET resistance | VEN/UVLO = 1 V, VSS/TRK = 0.1 V | 11 | Ω | ||
| VSS-FB | SS/TRK to FB offset | –15 | 0 | 15 | mV | |
| VSS-CLAMP | SS/TRK clamp voltage | VSS/TRK – VFB, VFB = 0.8 V | 115 | mV | ||
| POWER GOOD INDICATOR | ||||||
| PGUTH | FB upper threshold for PGOOD high to low | % of VREF, VFB rising | 106% | 108% | 110% | |
| PGLTH | FB lower threshold for PGOOD high to low | % of VREF, VFB falling | 90% | 92% | 94% | |
| PGHYS_U | PGOOD upper theshold hysteresis | % of VREF | 3% | |||
| PGHYS_L | PGOOD lower threshold hysteresis | % of VREF | 2% | |||
| TPG-RISE | PGOOD rising filter | FB to PGOOD rising edge | 25% | μs | ||
| TPG-FALL | PGOOD falling filter | FB to PGOOD falling edge | 25% | μs | ||
| VPG-OL | PGOOD low state output voltage | VFB = 0.9 V, IPGOOD = 2 mA | 150 | mV | ||
| IPG-OH | PGOOD high state leakage current | VFB = 0.8 V, VPGOOD = 13 V | 400 | nA | ||
| OSCILLATOR | ||||||
| FSW1 | Oscilator frequency – 1 | RRT = 100 kΩ | 100 | kHz | ||
| FSW2 | Oscillator frequency – 2 | RRT = 25 kΩ | 380 | 400 | 420 | kHz |
| FSW3 | Oscillator frequency – 3 | RRT = 12.5 kΩ | 780 | kHz | ||
| SYNCHRONIZATION INPUT AND OUTPUT | ||||||
| FSYNC | SYNCIN external clock frequency range | % of nominal frequency set by RRT | –20% | 50% | ||
| VSYNC-IH | SYNCIN input logic high | 2 | V | |||
| VSYNC-IL | SYNCIN input logic low | 0.8 | V | |||
| RSYNC-IN | SYNCIN input resistance | VSYNCIN = 3 V | 20 | kΩ | ||
| TSYNCI-PW | SYNCIN input minimum pulsewidth | Minimum high state or low state duration | 50 | ns | ||
| VSYNCO-OH | SYNCOUT high-state output voltage | ISYNCOUT = –1 mA (sourcing current) | 3 | V | ||
| VSYNCO-OL | SYNCOUT low-state output voltage | ISYNCOUT = 1 mA (sinking current) | 0.4 | V | ||
| TSYNCOUT | Delay from HO rising to SYNCOUT leading edge | VSYNCIN = 0 V, TS = 1/FSW, FSW set by RRT | TS/2 – 140 | ns | ||
| TSYNCIN | Delay from SYNCIN rising to HO leading edge | 50% to 50% | 150 | ns | ||
| GATE DRIVERS | ||||||
| RHO-UP | HO high state resistance, HO to BST | VBST – VSW = 7 V, IHO = –100 mA | 1.5 | Ω | ||
| RHO-DOWN | HO low state resistance, HO to SW | VBST – VSW = 7 V, IHO = 100 mA | 0.9 | Ω | ||
| RLO-UP | LO high state resistance, LO to VCC | VBST – VSW = 7 V, ILO = –100 mA | 1.5 | Ω | ||
| RLO-DOWN | LO low state resistance, LO to PGND | VBST – VSW = 7 V, ILO = 100 mA | 0.9 | Ω | ||
| IHOH, ILOH | HO, LO source current | VBST – VSW = 7 V, HO = SW, LO = AGND | 2.3 | A | ||
| IHOL, ILOL | HO, LO sink current | VBST – VSW = 7 V, HO = BST, LO = VCC | 3.5 | A | ||
| BOOTSTRAP DIODE AND UNDERVOLTAGE THRESHOLD | ||||||
| VBST-FWD | Diode forward voltage, VCC to BST | VCC to BST, BST pin sourcing 20 mA | 0.75 | 0.9 | V | |
| IQ-BST | BST to SW quiescent current, not switching | VSS/TRK = 0 V, VSW = 48 V, VBST = 54 V | 80 | μA | ||
| VBST-UV | BST to SW undervoltage detection | VBST – VSW falling | 3.4 | V | ||
| VBST-HYS | BST to SW undervoltage hysteresis | VBST – VSW rising | 0.42 | V | ||
| PWM CONTROL | ||||||
| tON(min) | Minimum controllable on-time | VBST – VSW = 7 V, HO 50% to 50% | 40 | 60 | ns | |
| tOFF(min) | Minimum off-time | VBST – VSW = 7 V, HO 50% to 50% | 140 | 200 | ns | |
| DC100kHz | Maximum duty cycle | FSW = 100 kHz, 6 V ≤ VVIN ≤ 60 V | 98 | 99 | % | |
| DC400kHz | FSW = 400 kHz, 6 V ≤ VVIN ≤ 60 V | 90 | 94 | % | ||
| VRAMP(min) | RAMP valley voltage (COMP at 0% duty cycle) | 300 | mV | |||
| kFF | PWM feedforward gain (VIN / VRAMP) | 6 V ≤ VVIN ≤ 100 V | 15 | V/V | ||
| OVER CURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING | ||||||
| IRS | ILIM source current, RSENSE mode | Low voltage detected at ILIM | 90 | 100 | 110 | μA |
| IRDSON | ILIM source current, RDS-ON mode | SW voltage detected at ILIM, TJ = 25°C | 180 | 200 | 220 | μA |
| IRDSONTC | ILIM current tempco | RDS-ON mode | 4500 | ppm/°C | ||
| IRSTC | ILIM current tempco | RSENSE mode | 0 | ppm/°C | ||
| VILIM-TH | ILIM comparator threshold at ILIM | –8 | –2 | 3.5 | mV | |
| SHORT CIRCUIT PROTECTION (SCP) – DUTY CYCLE CLAMP | ||||||
| VCLAMP-OS | Clamp offset voltage – no current limiting | COMP to duty cycle clamp voltage | 0.2 + VVIN/75 | V | ||
| VCLAMP-MIN | Minimum clamp voltage | Clamp voltage with continuous current limit | 0.3 + VVIN/150 | V | ||
| HICCUP MODE FAULT PROTECTION | ||||||
| CHICC-DEL | Hiccup mode activation delay | Clock cycles with current limiting before off-time activated | 128 | cycles | ||
| CHICCUP | Hiccup mode off time after activation | Clock cycles with no switching followed by SS/TRK release | 8192 | cycles | ||
| DIODE EMULATION / DCM OPERATION | ||||||
| VZCD-SS | Zero-cross detect (ZCD) soft-start ramp | ZCD threshold measured at SW pin 50 cycles after first HO pulse | 0 | mV | ||
| VZCD-DIS | Zero-cross detect disable threshold | ZCD threshold measured at SW pin 1000 cycles after first HO pulse | 200 | mV | ||
| VDEM-TH | Diode emulation zero-cross threshold | Measured at SW with VSW rising | –5 | 0 | 5 | mV |
| THERMAL SHUTDOWN | ||||||
| TSD | Thermal shutdown threshold | TJ rising | 175 | °C | ||
| TSD-HYS | Thermal shutdown hysteresis | 20 | °C | |||