Careful PCB layout is critical to achieve low EMI and stable power supply operation. If possible, mount all the power components on the top side of the board, making the high frequency current loops as small as possible, and follow these guidelines of good layout practices:

1. Keep the high-current paths short. This practice is essential for stable, jitter-free operation.
2. Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper (2 oz) can enhance full load efficiency by 1% or more.
3. Minimize current-sensing errors by routing CS and VOUT using a kelvin sensing directly across the current-sense resistor (Rsense).
4. Route high-speed switching nodes (HB, HO, LO, and SW) away from sensitive analog areas (FB, CS, and VOUT).

11.1 Layout Procedure

• Place the power components first, with ground terminals adjacent to the low-side FET. If possible, make all these connections on the top layer with wide, copper-filled areas.
• Mount the controller IC as close as possible to the high and low-side MOSFETs. Make the grounds and high and low-sided drive gate drive lines as short and wide as possible. Place the series gate drive resistor as close to the MOSFET as possible to minimize gate ringing.
• Locate the gate drive components (D1 and C17) together and near the controller IC; refer to Figure 41. Be aware that peak gate drive currents can be as high as 4 A. Average current up to 150 mA can flow from the VCC pin to the V_CC capacitor through the bootstrap diode to the bootstrap capacitor. Size the traces accordingly.
• Make the ground connections to the LM5140-Q1 controller as shown in Figure 43. Create a power grounds directly connected to all high-power components and an analog ground plane for sensitive analog components. The analog ground plane (AGND) and power ground plane (PGND1, and PGND2) must be connected at a single point directly under the IC (at the die attach pad or DAP).
• Figure 41 shows the schematic of the high frequency loops of one synchronous buck channel. The current flows through Q1 and Q2, through the power ground plane and back to VIN through the ceramic capacitors C11 and C12. This loop must be as small as possible to minimize EMI. Refer to Figure 42 For the recommended PCB layout.

11.2 Layout Example

Figure 41. Synchronous Buck Power Flow

Figure 42. Synchronous Buck High Frequency Current Path

Figure 43. AGND and PGND Connections

Figure 44. Top/Bottom PWM Layers