Section 7.3.11 describes the CBC current limiting functionality in detail. Figure 8-7 illustrates the current limiting block diagram of the LM5036 controller. These are the five resistors associated with the current limiting function of the half-bridge converter:

• R_CS
• R₃
• R₂
• R_LIM
• R₁

Because R₃ is equal to the equivalent resistance of R₁ and R₂ as given by Equation 13, there are four unknown resistor values to be determined.

The value of current sense resistor R_CS is determined based on the maximum power consumption requirement. Typically, the current sense resistor should consume less than 0.5% of the input power of the converter at the worst case scenario. The sense resistor conducts every alternate current pulse flowing in the primary winding. The power dissipated in the sense resistor is determined by Equation 61.

The RMS current flowing in the primary winding may be calculated using Equation 62.

Maximum loss in the current sense resistor will occur while maximum output current (I_LIM) is delivered from minimum input voltage (V_IN(min)). Evaluating Equation 62 gives Equation 63.

To achieve our target of dissipating less than 0.5% of maximum output power the current sense resistor must satisfy Equation 64.

In our example design the current sense resistor value selected is given in Equation 65.

The resistor R₁ is used to set the slope compensation magnitude. In LM5036 device, the slope of the compensation ramp is given by Equation 66. To eliminate sub-harmonic oscillation, set m_C to at least one-half the down-slope of output inductor current transformed to the primary side across the current sense resistor, as given by Equation 67 and Equation 68. To damp the sub-harmonic oscillation after one cycle, m_C must be set equal to one times the down-slope of the output inductor current. This configuration is known as deadbeat control. In LM5036 controller, the slope compensation signal is a saw-tooth current waveform of magnitude I_SLOPE at the oscillator frequency (twice the switching frequency).

where

• m_C is the slope of the compensation ramp
• I_SLOPE is the amplitude of the saw-tooth current signal used for slope compensation

where

• m_L is the down-slope of the output inductor current transformed to the primary side
• N_P is the number of turns for the primary winding of the main transformer
• N_S is the number of turns for the secondary winding of the main transformer
• V_O is the output voltage of the half-bridge converter
• L_O is the output inductor value of the half-bridge converter
• R_CS is the current sense resistor value

Substituting Equation 66 and Equation 67 into Equation 68 gives an expression for the minimum value for resistor R₁ to avoid sub-harmonic oscillation.

Doubling this value ensures deadbeat control. For this example design, the value given in Equation 70 are selected

Values have now been selected for both R_CS and R₁. Values for R_LIM and R₂ are yet to be determined. These values define the peak current limit threshold and how this level varies with input voltage. Equation 20, Equation 21 and Equation 25 define the relationship between peak primary current limit and maximum output current. For this design example ignore I_BiasOffset and V_CSOffset, because these parameters have only a small effect on output current limit. Setting these parameters to zero calculates Equation 71, Equation 72 and Equation 73.

The output current limit varies with input voltage. This design example limits the output current to I_LIM at the extremes of input voltage giving Equation 74 and Equation 75. This value limits the spread of output current limit across the range of input voltage.

Solving Equation 74 and Equation 75 simultaneously yields values for resistors R_LIM and R₂.

Having determined values for R₁ and R₂, the value of resistor R₃ is fixed by Equation 13.

The selected values for R₂ and R_LIM are given in Equation 78. Figure 8-9 presents the measured output current limit vs input voltage for the circuit presented in Figure 8-1. Figure 8-9 also presents the output current limit vs line for the same circuit predicted by Equation 71, Equation 72 and Equation 73. There is good agreement between measured and predicted results.

If the magnitude of the leading-edge spike is excessive, add an additional filter capacitor C_F to form an RC filter with R₁, to reduce the high-frequency noise spike. Both the leading-edge blanking (t_CSBLK) and the RC filter help to prevent false triggering of the CBC current limiting operation.

The circuit connected to the CS_POS pin may be approximated by the simplified circuit shown in Figure 8-10.

The voltage across the current sense resistor during the conduction period of the low-side MOSFET is represented by Equation 79.

Where I_P0 is the primary current at the start of the on period of the lower switch, and m is the slope of the primary current during the on period.

The voltage across capacitor C_F for the circuit shown is expressed by Equation 82.

Let us assume that the on period of the lower switch is more than four times longer than the time constant made up of C_F and R₁. In this case the exponential term of Equation 82 tends to zero and the voltage across capacitor C_F at the end of the t_ON period may be expressed by Equation 83.

Comparing Equation 79 and Equation 83 shows that capacitor C_F introduces an error in the sensed peak current given by Equation 84.

Hence, to ensure the error introduced by the filter capacitor is less than 2%, the value of capacitor C_F should not exceed the value given by Equation 85.

The Excel Calculator Tool can be used to facilitate the process of calculating all the external CBC component values.