10.1 Layout Guidelines

In addition to following general power management IC layout guidelines (star grounding, minimal current loops, reasonable impedance levels, and so on) layout for the LM5021 should take into account the following:

• If possible, a ground plane should be used to minimize the voltage drop on the ground circuit and the noise introduced by parasitic inductances in individual traces.
• A decoupling capacitor is required for both the VIN pin and VCC pin and both should be returned to GND as close to the IC as possible. VIN is the more critical capacitor and should take first priority when connecting to GND as close as possible to the IC.
• The timing setting components such as the RT pin resistor, SS pin capacitor should be directly connected to the ground plane or returned directly to the GND pin on their own traces.
• The CS pin filter capacitor should be as close to the IC possible and grounded right at the IC ground pin. This ensures the best filtering effect and minimizes the chance of current sense pin malfunction.
• Gate driver loop area should be minimized to reduce the EMI noise because of the high di/dt current in the loop.

10.2 Layout Example

Figure 26. Layout Example

Figure 27. Top Side View

Figure 28. Bottom Side View