ZHCSLI5 September 2020 LM34966-Q1
PRODUCTION DATA
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | BIAS | P | Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND. |
| 2 | NC | - | No electrical contact |
| 3 | VCC | P | Output of the internal VCC regulator and supply voltage input of the MOSFET driver. Connect a ceramic bypass capacitor from this pin to PGND. |
| 4 | GATE | O | N-channel MOSFET gate drive output. Connect directly to the gate of the N-channel MOSFET through a short, low inductance path. |
| 5 | PGND | G | Power ground pin. Connect directly to the ground connection of the sense resistor through a low inductance wide and short path. |
| 6 | AGND | G | Analog ground pin. Connect directly to the analog ground plane through a wide and short path. |
| 7 | CS | I | Current sense input pin. Connect to the positive side of the current sense resistor through a short path. |
| 8 | COMP | O | Output of the internal transconductance error amplifier. Connect the loop compensation components between this pin and ground plane. |
| 9 | VDD | I | Input of the internal logic. Connect directly to VCC. |
| 10 | FB | I | Inverting input of the error amplifier. Connect a voltage divider from the output to this pin to set output voltage in boost/SEPIC/non-isolated flyback topologies. Connect the low-side feedback resistor to AGND. |
| 11 | SS | I | Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. Connect the ground connection of the capacitor to AGND. |
| 12 | RT | I | Switching frequency setting pin. The switching frequency is programmed by a single resistor between RT and AGND. |
| 13 | PGOOD | O | Power-good indicator. An open-drain output which goes low if FB is below the undervoltage threshold. Connect a pullup resistor to the system voltage rail. If not used, leave the pin floating. |
| 14 | EN/UVLO/SYNC | I | Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a resistor divider. The internal clock can be synchronized to an external clock by applying a negative pulse signal into the EN/UVLO/SYNC pin. This pin must not be left floating. Connect to BIAS pin if not used. Connect the low-side UVLO resistor to AGND. |
| — | EP | — | Exposed pad of the package. The exposed pad must be connected to AGND and the large ground copper plane to decrease thermal resistance. |