SNVS561G September 2008 – September 2015 LM3150
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Typical Application Schematic
- 5 Revision History
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|14
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- PWP|14
訂購信息
11 Layout
11.1 Layout Guidelines
It is good practice to layout the power components first, such as the input and output capacitors, FETs, and inductor. The first priority is to make the loop between the input capacitors and the source of the low-side FET to be very small and tie the grounds of the low-side FET and input capacitor directly to each other and then to the ground plane through vias. As shown in Figure 21 when the input capacitor ground is tied directly to the source of the low-side FET, parasitic inductance in the power path, along with noise coupled into the ground plane, are reduced.
The switch node is the next item of importance. The switch node should be made only as large as required to handle the load current. There are fast voltage transitions occurring in the switch node at a high frequency, and if the switch node is made too large it may act as an antennae and couple switching noise into other parts of the circuit. For high power designs, it is recommended to use a multilayer board. The FETs are going to be the largest heat generating devices in the design, and as such, care should be taken to remove the heat. On multilayer boards using exposed-pad packages for the FETs such as the power-pak SO-8, vias should be used under the FETs to the same plane on the interior layers to help dissipate the heat and cool the FETs. For the typical single FET Power-Pak type FETs, the high-side FET DAP is VIN. The VIN plane should be copied to the other interior layers to the bottom layer for maximum heat dissipation. Likewise, the DAP of the low-side FET is connected to the SW node and the SW node shape should be duplicated to the other PCB layers for maximum heat dissipation.
See the Evaluation Board application note AN-1900 (SNVA371) for an example of a typical multilayer board layout, and the Demonstration Board Reference Design Application Note for a typical 2-layer board layout. Each design allows for single-sided component mounting.
Figure 21. Schematic of Parasitics
11.2 Layout Example
Figure 22. PCB Placement of Power Stage