Equation 13.

Equation 14.

R_FB2 = 22.6 kΩ, nearest 1% standard value.

t_OFF should meet the following criteria:

At the maximum switching frequency of 687 kHz, which is limited by the minimum on-time, the off-time of 654 ns is less than 725 ns. Therefore the switching frequency should be reduced and meet the following criteria:

A switching frequency is arbitrarily chosen at 500 kHz which should allow for reasonable size components and satisfies the requirements above.

f_S = 500 kHz

Using f_S = 500 kHz R_ON can be calculated as follows:

Next, check the desired minimum input voltage for R_ON using Figure 15. This design will meet the desired minimum input voltage of 6 V.

The voltage rating on the output capacitor should be greater than or equal to the output voltage. As a rule of thumb most capacitor manufacturers suggests not to exceed 90% of the capacitor rated voltage. In the case of multilayer ceramics the capacitance will tend to decrease dramatically as the applied voltage is increased towards the capacitor rated voltage. The capacitance can decrease by as much as 50% when the applied voltage is only 30% of the rated voltage. The chosen capacitor should also be able to handle the rms current which is equal to:

Equation 32.

For this design the chosen ripple current ratio, r = 0.3, represents the ratio of inductor peak-to-peak current to load current I_OUT. A good starting point for ripple ratio is 0.3 but it is acceptable to choose r between 0.25 to 0.5. The nomographs in this datasheet all use 0.3 as the ripple current ratio.

Equation 33.

Minimum output capacitance is:

The maximum ESR allowed to prevent overvoltage protection during normal operation is:

For this design a feed-forward capacitor will be used to help minimize output ripple.

The minimum ESR must meet both of the following criteria:

Based on the above criteria two 150-µF polymer aluminum capacitors with a ESR = 12 mΩ each for a effective ESR in parallel of 6 mΩ was chosen from Panasonic. The part number is EEF-UE0J101P.

From Step 5 the capacitor chosen in ESR is small enough that we should use a feed-forward capacitor. This is calculated from:

Equation 47.

Let C_ff = 270 pF, which is the closest next standard value.

The LM3150 controller is designed to drive N-channel MOSFETs. For a maximum input voltage of 24 V we should choose N-channel MOSFETs with a maximum drain-source voltage, V_DS, greater than 1.2 x 24 V = 28.8 V. FETs with maximum V_DS of 30 V will be the first option. The combined total gate charge Q_gtotal of the high-side and low-side FET should satisfy the following:

Where I_VCCL is the minimum current limit of VCC, over the temperature range, specified in the Electrical Characteristics table. The MOSFET gate charge Q_g is gathered from reading the V_GS vs Q_g curve of the MOSFET datasheet at the V_GS = 5 V for the high-side, M1, MOSFET and V_GS = 6 V for the low-side, M2, MOSFET.

The Renesas MOSFET RJK0305DPB has a gate charge of 10 nC at V_GS = 5 V, and 12 nC at V_GS = 6 V. This combined gate charge for a high-side, M1, and low-side, M2, MOSFET 12 nC + 10 nC = 22 nC is less than 130 nC calculated Q_gtotal.

The calculated MOSFET power dissipation must be less than the max allowed power dissipation, Pdmax, as specified in the MOSFET data sheet. An approximate calculation of the FET power dissipated Pd, of the high-side and low-side FET is given by:

High-Side MOSFET

Equation 51.

The max power dissipation of the RJK0305DPB is rated as 45 W for a junction temperature that is 125°C higher than the case temperature and a thermal resistance from the FET junction to case, θ_JC, of 2.78°C/W. When the FET is mounted onto the PCB, the PCB will have some additional thermal resistance such that the total system thermal resistance of the FET package and the PCB, θ_JA, is typically in the range of 30°C/W for this type of FET package. The max power dissipation, Pdmax, with the FET mounted onto a PCB with a 125°C junction temperature rise above ambient temperature and θ_JA = 30°C/W, can be estimated by:

The system calculated Pdh of 0.674 W is much less than the FET Pdmax of 4.1 W and therefore the RJK0305DPB max allowable power dissipation criteria is met.

Low-Side MOSFET

Primary loss is conduction loss given by:

Pdl is also less than the Pdmax specified on the RJK0305DPB MOSFET data sheet.

However, it is not always necessary to use the same MOSFET for both the high-side and low-side. For most applications it is necessary to choose the high-side MOSFET with the lowest gate charge and the low-side MOSFET is chosen for the lowest allowed R_DS(ON). The plateau voltage of the FET V_GS vs Q_g curve must be less than VCC - 750 mV.

The current limit resistor, R_LIM, is calculated by estimating the R_DS(ON) of the low-side FET at the maximum junction temperature of 100°C. By choosing to go into current limit when the average output load current is 20% higher than the output load current of 12A while the inductor ripple current ratio is 1/3 of the load current will make I_CL= 10.4 A. Then the following calculation of R_LIM is:

Let R_LIM = 1.91 kΩ which is the next standard value.

The input capacitor should be chosen so that the voltage rating is greater than the maximum input voltage which for this example is 24 V. Similar to the output capacitor, the voltage rating needed will depend on the type of capacitor chosen. The input capacitor should also be able to handle the input rms current, which is a maximum of approximately 0.5 x I_OUT. For this example the rms input current is approximately 0.5 x 12 A = 6 A.

The minimum capacitance with a maximum 5% input ripple ΔV_IN-MAX = (0.05 x 12) = 0.6 V:

To handle the large input rms current 2 ceramic capacitors are chosen at 10 µF each with a voltage rating of 50 V and case size of 1210. Each ceramic capacitor is capable of handling 3 A of rms current. A aluminum electrolytic of 5 times the combined input capacitance, 5 x 20 µF = 100 µF, is chosen to provide input voltage filter damping because of the low ESR ceramic input capacitors.

C_BYP = 0.1µF ceramic with a voltage rating greater than maximum V_IN

The soft start-time should be greater than the input voltage rise time and also satisfy the following equality to maintain a smooth transition of the output voltage to the programmed regulation voltage during startup. The desired soft-start time, tss, of 5 ms also must satisfy the equality in Equation 12, by using the chosen component values through the previous steps as shown below:

Because the desired soft-start time satisfies the equality in Equation 12, the soft start capacitor is calculated as:

Let C_SS = 0.068 µF, which is the next closest standard value. This should be a ceramic cap with a voltage rating greater than 10 V.

C_VCC = 4.7-µF ceramic with a voltage rating greater than 10 V

C_EN = 1000-pF ceramic with a voltage rating greater than 10 V

C_BST = 0.47-µF ceramic with a voltage rating greater than 10 V

Equation 59.

where

• R_FB1 is the bottom resistor
• R_FB2 is the top resistor

The available frequency range for a given input voltage range, is determined by the duty-cycle, D = V_OUT/V_IN, and the minimum t_ON and t_OFF times as specified in the Electrical Characteristics table. The maximum frequency is thus, f_smax = D_min/t_ON-MIN. Where D_min=V_OUT/V_IN-MAX, is the minimum duty-cycle. The off-time will need to be less than the minimum off-time t_OFF as specified in the Electrical Characteristics table plus any turnoff and turnon delays of the MOSFETs which can easily add another 200 ns. The minimum off-time will occur at maximum duty cycle D_max and will determine if the frequency chosen will allow for the minimum desired input voltage. The requirement for minimum off-time is t_OFF= (1–D_max)/f_s ≥ (t_OFF-MIN + 200 ns). If t_OFF does not meet this requirement it will be necessary to choose a smaller switching frequency f_S.

Choose R_ON so that the switching frequency at your typical input voltage matches your f_S chosen above using the following formula:

Use Figure 15 to determine if the calculated R_ON will allow for the minimum desired input voltage. If the minimum desired input voltage is not met, recalculate R_ON for a lower switching frequency.

Figure 15. Minimum V_IN vs. V_OUT
I_OUT = 10 A

To use the nomograph in Figure 16, calculate the inductor volt-microsecond constant ET from the following formula:

Equation 62.

where

• f_s is in kHz units

The intersection of the Load Current and the Volt-microseconds lines on the chart below will determine which inductors are capable for use in the design. Figure 16 shows a sample of parts that can be used. The offline calculator tools and WEBENCH will fully calculate the requirements for the components needed for the design.

Figure 16. Inductor Nomograph

Typical hysteretic COT converters similar to the LM3150 controller require a certain amount of ripple that is generated across the ESR of the output capacitor and fed back to the error comparator. Emulated Ripple Mode control built into the LM3150 controller will recreate a similar ripple signal and thus the requirement for output capacitor ESR will decrease compared to a typical Hysteretic COT converter. The emulated ripple is generated by sensing the voltage signal across the low-side FET and is then compared to the FB voltage at the error comparator input to determine when to initiate the next on-time period.

The maximum ESR allowed to prevent overvoltage protection during normal operation is:

ET_min is calculated using V_IN-MIN

A_f = V_OUT / 0.6 if there is no feed-forward capacitor used

A_f = 1 if there is a feed-forward capacitor used

The minimum ESR must meet both of the following criteria:

ET_max is calculated using V_IN-MAX.

Any additional parallel capacitors should be chosen so that their effective impedance will not negatively attenuate the output ripple voltage.

Certain applications may require a feed-forward capacitor for improved stability and easier selection of available output capacitance. Use the following equation to calculate the value of C_ff.

The high-side and low-side FETs must have a drain to source (V_DS) rating of at least 1.2 x V_IN.

Use the following equations to calculate the desired target value of the low-side FET R_DS(ON) for current limit.

Equation 69.

The gate drive current from VCC must not exceed the minimum current limit of VCC. The drive current from VCC can be calculated with:

The plateau voltage of the FET V_GS vs Q_g curve, as shown in Figure 17, must be less than VCC - 750 mV.

Figure 17. Typical MOSFET Gate Charge Curve

See following design example for estimated power dissipation calculation.

The main parameters for the input capacitor are the voltage rating, which must be greater than or equal to the maximum DC input voltage of the power supply, and its rms current rating. The maximum rms current is approximately 50% of the maximum load current.

Equation 72.

where

• ΔV_IN-MAX is the maximum allowable input ripple voltage. A good starting point for the input ripple voltage is 5% of V_IN

When using low ESR ceramic capacitors on the input of the LM3150 controller, a resonant circuit can be formed with the impedance of the input power supply and parasitic impedance of long leads/PCB traces to the LM3150 input capacitors. TI recommends using a damping capacitor under these circumstances, such as aluminum electrolytic that will prevent ringing on the input. The damping capacitor should be chosen to be approximately five times greater than the parallel ceramic capacitors combination. The total input capacitance should be greater than 10 times the input inductance of the power supply leads/PCB trace. The damping capacitor should also be chosen to handle its share of the rms input current which is shared proportionately with the parallel impedance of the ceramic capacitors and aluminum electrolytic at the LM3150 switching frequency.

The C_BYP capacitor should be placed directly at the VIN pin. The recommended value is 0.1 µF.

Equation 73.

where

• t_ss is the soft-start time in seconds
• V_ref = 0.6V

C_VCC should be placed directly at the VCC pin with a recommended value of 1 µF to 4.7 µF. C_BST creates a voltage used to drive the gate of the high-side FET. It is charged during the SW off-time. The recommended value for C_BST is 0.47 µF. The EN bypass capacitor, C_EN, recommended value is 1000 pF when driving the EN pin from open-drain type of signal.