9.1.2.1 Filter Inductor

For most applications, choose an inductance such that the inductor ripple current, ΔI_L, is between 20% and 40% of the maximum dc output current. Choose the inductance using Equation 10:

Equation 10.

Check the inductor datasheet to ensure that the inductor's saturation current is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that an inductor's saturation current generally deceases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation.

9.1.2.2 Output Capacitors

Ordinarily, the regulator’s output capacitor energy store combined with the control loop response are prescribed to maintain the integrity of the output voltage within both the static and dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics – equivalent series resistance (ESR) and equivalent series inductance (ESL) – take increasing precedence in shaping the regulator’s load transient response as the output current ramp amplitude and slew rate increase.

So, the output capacitor, C_OUT, exists to filter the inductor ripple current and provide a reservoir of charge for step load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events.

Based on the static specification of peak-to-peak output voltage ripple denoted by ΔV_O, choose an output capacitance that is larger than

Equation 11.

Figure 38 conceptually illustrates the relevant current waveforms during both load step-up and step-down transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load-on transient. Similarly, during and after a load-off transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that needs to be depleted as quickly as possible.

Figure 38. Load Transient Response Representation Showing C_OUT Charge Surplus Or Deficit.

In a typical regulator application of 12-V input to low output voltage (say 1.2 V), it should be recognized that the load-off transient represents worst-case. In that case, the steady-state duty cycle is approximately 10% and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –V_OUT/L. Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and rein in the voltage overshoot.

To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as ΔV_overshoot with step reduction in output current given by ΔI_o), the output capacitance should be larger than

Equation 12.

The ESR of a capacitor is provided in the manufacturer’s datasheet either explicitly as a specification or implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some ESR and ESL as well. Ceramic output capacitors, on the other hand, are such that the impedances related to the ESR and ESL are small at the switching frequency, and the capacitive impedance dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied voltage and operating temperature.

Ignoring the ESR term in Equation 11 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. One to four 100-µF, 6.3-V, X5R capacitors in 1206 or 1210 footprint is a common choice. Use Equation 12 to quantify if additional capacitance is necessary to meet the load-off transient overshoot specification.

A composite implementation of ceramic and electrolytic capacitors highlights the rationale of paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range of interest. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance provides low-frequency energy storage to cope with load-transient demands.

9.1.2.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage while switching-frequency ac current to the buck power stage. It is generally recommended to use X5R or X7R dielectric ceramic capacitors, thus providing low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET.

The input capacitors' RMS current is given by Equation 13.

Equation 13.

The highest requirement for input capacitor RMS current rating occurs at D = 0.5, at which point the RMS current rating should be greater than half the output current.

Ideally, the dc component of input current is provided by the input voltage source and the ac component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude I_o−I_IN during the D interval and sinks I_IN during the 1−D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component of ac ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak ripple voltage amplitude is given by Equation 14.

Equation 14.

The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔV_IN, is given by Equation 15.

Equation 15.

Low ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. One bulk capacitor of sufficiently high current rating and one or two 10-μF 25-V X7R ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current rating and operating temperature.

9.1.2.4 Power MOSFETs

The choice of MOSFET has significant impact on DC-DC regulator performance. A MOSFET with low on-state resistance, R_DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R_DS(on) of a MOSFET, the higher the gate charge, Q_G, and vice versa. As a result, the product R_DS(on)*Q_G is commonly specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting MOSFET selection in an LM27403 application are as follows:

• R_DS(on) at V_GS = 4.5 V;
• Drain-source voltage rating, BV_DSS, typically 25 V or 30 V;
• Gate charge parameters at V_GS = 4.5 V;
• Body diode reverse recovery charge, Q_RR;
• Gate threshold voltage, V_GS(th), derived from the plateau in the Q_G vs. V_GS curve in the MOSFET's datasheet. V_GS(th) should be in the range 2 V to 3 V such that the MOSFET is adequately enhanced when on and margin against Cdv/dt shoot-through exists when off.

The MOSFET-related power losses are summarized by the equations presented in Table 2. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances, are not discussed. Consult the LM27403 Quick-start Design Tool to assist with power loss calculations.

Table 2. Buck Regulator MOSFET Power Losses

Power Loss Mode	High-Side MOSFET	Low-Side MOSFET
Conduction (2)		(3)
Switching		Negligible
Gate Drive(1)
Body Diode Conduction	N/A
Body Diode Reverse Recovery

(1) Gate drive loss is not dissipated in the MOSFET but rather in the LM27403's integrated drivers.

(2) MOSFET R_DS(on) has a positive temperature coefficient of approximately 4000 ppm/°C. The MOSFET junction temperature, T_J, and its rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance.

(3) D' = 1–D is the duty cycle complement.

The high-side (control) MOSFET carries the inductor current during the PWM on time (or D interval) and typically incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching and typically two-thirds of the net loss attributed to body diode reverse recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just commutates from the channel to the body diode or vice versa during the deadtime. The LM27403, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.

In high input voltage and low output voltage applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low R_DS(on). In cases where the conduction loss is too high or the target R_DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery.

The LM27403 is well matched to TI's comprehensive portfolio of 25-V and 30-V NexFET™ family of power MOSFETs. In fact, the LM27403 is ideally suited to driving the Power Block NexFET™ modules with integrated high-side and low-side MOSFETs. Excellent efficiency is obtained by virtue of reduced parasitics and exemplary thermal performance of the Power Block MOSFET implementation. See the Typical Applications section for more details.

Table 3. Regulator Poles and Zeros

Power Stage Poles	Power Stage Zeros	Compensator Poles	Compensator Zeros
	(1)
	(2)

Table 4. Buck Regulator Small-Signal Analysis

PARAMETER	EXPRESSION
Open-loop transfer function
Duty-cycle-to-output transfer function
Compensator transfer function(1)
Modulator transfer function

Table 5. Compensation Component Selection

RESISTORS	CAPACITORS

9.2.1.1 Design Requirements

The schematic diagram of a 25-A regulator is given in Figure 41. In this example, the target full-load efficiencies are 91% and 97% at 1.2-V and 5.3-V output voltages, respectively, based on a nominal input voltage of 12 V that ranges from 6.5 V to 20 V. Output voltage is adjusted simply by changing R_FB2. The switching frequency is set by means of a synchronization signal at 300 kHz, and free-running switching frequency (in the event that the synchronization signal is removed) is set to 250 kHz by resistor R_FADJ. In terms of control loop performance, the target loop crossover frequency is 45 kHz with a phase margin in excess of 50°. The output voltage soft-start time is 8 ms.

9.2.1.2 Detailed Design Procedure

The design procedure for an LM27403-based converter for a given application is streamlined by using the LM27403 Quick-Start Design Tool available as a free download, or by availing of TI's WEBENCH® Designer online software. Such tools are complemented by the availability of two LM27403 evaluation module (EVM) designs as well as numerous LM27403 reference designs populated in TI Designs™ reference design library.

The current limit setpoint in this design is set at 28.5 A, based on resistor R_ISET and the inductor DCR (1.1 mΩ typ at 25°C). Of course, the current limit setpoint should always be selected such that the operating current level does not exceed the saturation current specification of the chosen inductor. The component values for the DCR sense network (R_S and C_S in Figure 41) are chosen based on making the R_SC_S product approximately equal to L/R_dcr, as recommended in the Current Sensing: CS+ and CS– section.

The selected buck converter powertrain components are cited in Table 6, and many of the components are available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching power loss, as discussed in detail in the Power MOSFETs section.

9.2.1.3 Application Curves

Figure 42. Efficiency vs. Output Current at V_IN = 12 V

Figure 44. Load Transient Response at V_OUT = 1.2 V, I_OUT 0A to 10A at 2A/µs

Figure 43. Efficiency vs. Output Current at V_OUT = 1.2 V

Figure 45. Startup Characteristic with V_IN stepped from 0 V to 12 V, V_OUT = 1.2 V, 70-mΩ Load

9.2.2.1 Design Requirements

The schematic diagram of a 600-kHz, 30-A regulator is given in Figure 46. The powertrain components are listed in Table 7.

Table 7. List of Materials for Design 2

9.2.2.2 Detailed Design Procedure

A high power density, high efficiency solution is feasible by using TI NexFET™ Power Block module CSD87350Q5D (dual asymmetric MOSFETs in a SON 5-mm x 6-mm package) together with and low-DCR ferrite inductor and all-ceramic capacitor design. The design occupies 20 mm x 15 mm on a single-sided PCB. Knowing the cumulative resistance of the inductor DCR and Power Block MOSFET SW clip (approximately 1 mΩ at 25°C), resistor R_ISET positions the current limit setpoint at 28A. The output voltage is adjusted by choosing the resistance of R_FB2 appropriately. Resistors R_TRK1 and R_TRK2 connected to the SS/TRACK pin define a coincidental tracking startup sequence from a master power supply, V_TRACK.

Additional input and/or output capacitance can be added if needed, but adjust the compensation if C_OUT changes. The T_GR pin of the Power Block MOSFET serves as a kelvin connection to the source of the high-side MOSFET and represents the return path for the high-side gate drive. Along with bootstrap capacitor, C_BOOT, T_GR is connected to the LM27403's SW pin.

9.2.2.3 Application Curves

Figure 47. Efficiency vs. Output Current at V_IN = 12 V

Table 8. List of Materials for Design 3

Table 9. List of Materials for Design 4

Table 10. List of Materials for Design 5