Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout, small-signal components are typically placed on the bottom side (component side). Insert at least one inner plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
The DC/DC regulator has several high-current
loops. Minimize the area of these loops to suppress generated switching noise
and optimize switching performance.
Loop 1: The most
important loop area to minimize is the path from the input capacitor or
capacitors through the high- and low-side MOSFETs, and back to the
capacitor or capacitors through the ground connection. Connect the input
capacitor or capacitors negative terminal close to the source of the
low-side MOSFET (at ground). Similarly, connect the input capacitor or
capacitors positive terminal close to the drain of the high-side MOSFET
(at VIN). Refer to loop 1 of GUID-BFD90C37-2547-45D4-942D-126A85B9F387.html#SNVSAI48000.
Another loop, not as
critical as loop 1, is the path from the low-side MOSFET through the
inductor and output capacitor or capacitors, and back to source of the
low-side MOSFET through ground. Connect the source of the low-side
MOSFET and negative terminal of the output capacitor or capacitors at
ground as close as possible.
The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and wide. However, the SW connection is a source of injected EMI and thus must not be too large.
Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including pad geometry and solder paste stencil design.
The SW pin connects to the switch node of the power conversion stage and acts as the return path for the high-side gate driver. The parasitic inductance inherent to loop 1 in GUID-BFD90C37-2547-45D4-942D-126A85B9F387.html#SNVSAI48000 and the output capacitance (COSS) of both power MOSFETs form a resonant circuit that induces high frequency (greater than 50 MHz) ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then include snubber components as needed.