ZHCSNC7 December 2021 LM25148
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Input Voltage Range (VIN)
- 8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
- 8.3.3 Precision Enable (EN)
- 8.3.4 Power-Good Monitor (PG)
- 8.3.5 Switching Frequency (RT)
- 8.3.6 Dual Random Spread Spectrum (DRSS)
- 8.3.7 Soft Start
- 8.3.8 Output Voltage Setpoint (FB)
- 8.3.9 Minimum Controllable On Time
- 8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
- 8.3.11 Slope Compensation
- 8.3.12 Inductor Current Sense (ISNS+, VOUT)
- 8.3.13 Hiccup Mode Current Limiting
- 8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
- 8.3.15 Output Configurations (CNFG)
- 8.3.16 Single-Output Dual-Phase Operation
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1
Design 1 – High Efficiency 2.1-MHz Synchronous
Buck Regulator
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Custom Design With WEBENCH? Tools
- 9.2.1.2.2 Custom Design With Excel Quickstart Tool
- 9.2.1.2.3 Buck Inductor
- 9.2.1.2.4 Current-Sense Resistance
- 9.2.1.2.5 Output Capacitors
- 9.2.1.2.6 Input Capacitors
- 9.2.1.2.7 Frequency Set Resistor
- 9.2.1.2.8 Feedback Resistors
- 9.2.1.2.9 Compensation Components
- 9.2.1.3 Application Curves
- 9.2.2 Design 2 – High Efficiency 440-kHz Synchronous Buck Regulator
- 9.2.3 Design 3 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
- 9.2.1
Design 1 – High Efficiency 2.1-MHz Synchronous
Buck Regulator
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RGY|24
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGY|24
訂購信息
9.1.2 Error Amplifier and Compensation
Figure 9-3 shows a type-ll compensator using a transconductance error amplifier (EA). The dominant pole of the EA open-loop gain is set by the EA output resistance, RO-EA, and effective bandwidth-limiting capacitance, CBW, as shown by Equation 25.
The EA high-frequency pole is neglected in the above expression. Equation 26 calculates the compensator transfer function from output voltage to COMP node, including the gain contribution from the (internal or external) feedback resistor network.
where
- VREF is the feedback voltage reference of 0.8 V.
- gm is the EA gain transconductance of 1200 μS.
- RO-EA is the error amplifier output impedance of 64 M?.
The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically, RCOMP << RO-EA and CCOMP >> CBW and CHF, so the approximations are valid.
Figure 9-3 Error Amplifier
and Compensation Network