ZHCSNC7 December 2021 LM25148
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Input Voltage Range (VIN)
- 8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
- 8.3.3 Precision Enable (EN)
- 8.3.4 Power-Good Monitor (PG)
- 8.3.5 Switching Frequency (RT)
- 8.3.6 Dual Random Spread Spectrum (DRSS)
- 8.3.7 Soft Start
- 8.3.8 Output Voltage Setpoint (FB)
- 8.3.9 Minimum Controllable On Time
- 8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
- 8.3.11 Slope Compensation
- 8.3.12 Inductor Current Sense (ISNS+, VOUT)
- 8.3.13 Hiccup Mode Current Limiting
- 8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
- 8.3.15 Output Configurations (CNFG)
- 8.3.16 Single-Output Dual-Phase Operation
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1
Design 1 – High Efficiency 2.1-MHz Synchronous
Buck Regulator
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Custom Design With WEBENCH? Tools
- 9.2.1.2.2 Custom Design With Excel Quickstart Tool
- 9.2.1.2.3 Buck Inductor
- 9.2.1.2.4 Current-Sense Resistance
- 9.2.1.2.5 Output Capacitors
- 9.2.1.2.6 Input Capacitors
- 9.2.1.2.7 Frequency Set Resistor
- 9.2.1.2.8 Feedback Resistors
- 9.2.1.2.9 Compensation Components
- 9.2.1.3 Application Curves
- 9.2.2 Design 2 – High Efficiency 440-kHz Synchronous Buck Regulator
- 9.2.3 Design 3 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
- 9.2.1
Design 1 – High Efficiency 2.1-MHz Synchronous
Buck Regulator
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RGY|24
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGY|24
訂購信息
8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
The LM25148 contains gate drivers and an associated high-side level shifter to drive the external N-channel power MOSFETs. The high-side gate driver works in conjunction with an internal bootstrap diode DBOOT and bootstrap capacitor CBOOT. During the conduction interval of the low-side MOSFET, the SW voltage is approximately 0 V and CBOOT charges from VCC through the internal DBOOT. TI recommends a 0.1-μF ceramic capacitor connected with short traces between the CBOOT and SW pins.
The HO and LO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and LO) are never on at the same time, preventing cross conduction. Before the LO driver output is allowed to turn on, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below 2 V typical. LO is allowed to turn on after a small delay (HO fall to LO rising delay). Similarly, the HO turn-on is delayed until the LO voltage has dropped below 2 V. This technique ensures adequate dead-time for any size N-channel power MOSFET implementations, including parallel MOSFET configurations.
Caution is advised when adding series gate resistors, as this can impact the effective dead-time. The selected high-side MOSFET determines the appropriate bootstrap capacitance value CBOOT in accordance with Equation 11.
where
- QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage.
- ΔVCBOOT is the voltage variation of the high-side MOSFET driver after turn-on.
To determine CBOOT, choose ΔVCBOOT such that the available gate drive voltage is not significantly impacted. An acceptable range of ΔVCBOOT is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic capacitor, typically 0.1 μF. Use high-side and low-side MOSFETs with logic-level gate threshold voltages.