ZHCSDM9A December 2014 – March 2018 LDC1612 , LDC1614
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Register List
- 7.6.2 Address 0x00, DATA0_MSB
- 7.6.3 Address 0x01, DATA0_LSB
- 7.6.4 Address 0x02, DATA1_MSB
- 7.6.5 Address 0x03, DATA1_LSB
- 7.6.6 Address 0x04, DATA2_MSB (LDC1614 only)
- 7.6.7 Address 0x05, DATA2_LSB (LDC1614 only)
- 7.6.8 Address 0x06, DATA3_MSB (LDC1614 only)
- 7.6.9 Address 0x07, DATA3_LSB (LDC1614 only)
- 7.6.10 Address 0x08, RCOUNT0
- 7.6.11 Address 0x09, RCOUNT1
- 7.6.12 Address 0x0A, RCOUNT2 (LDC1614 only)
- 7.6.13 Address 0x0B, RCOUNT3 (LDC1614 only)
- 7.6.14 Address 0x0C, OFFSET0
- 7.6.15 Address 0x0D, OFFSET1
- 7.6.16 Address 0x0E, OFFSET2 (LDC1614 only)
- 7.6.17 Address 0x0F, OFFSET3 (LDC1614 only)
- 7.6.18 Address 0x10, SETTLECOUNT0
- 7.6.19 Address 0x11, SETTLECOUNT1
- 7.6.20 Address 0x12, SETTLECOUNT2 (LDC1614 only)
- 7.6.21 Address 0x13, SETTLECOUNT3 (LDC1614 only)
- 7.6.22 Address 0x14, CLOCK_DIVIDERS0
- 7.6.23 Address 0x15, CLOCK_DIVIDERS1
- 7.6.24 Address 0x16, CLOCK_DIVIDERS2 (LDC1614 only)
- 7.6.25 Address 0x17, CLOCK_DIVIDERS3 (LDC1614 only)
- 7.6.26 Address 0x18, STATUS
- 7.6.27 Address 0x19, ERROR_CONFIG
- 7.6.28 Address 0x1A, CONFIG
- 7.6.29 Address 0x1B, MUX_CONFIG
- 7.6.30 Address 0x1C, RESET_DEV
- 7.6.31 Address 0x1E, DRIVE_CURRENT0
- 7.6.32 Address 0x1F, DRIVE_CURRENT1
- 7.6.33 Address 0x20, DRIVE_CURRENT2 (LDC1614 only)
- 7.6.34 Address 0x21, DRIVE_CURRENT3 (LDC1614 only)
- 7.6.35 Address 0x7E, MANUFACTURER_ID
- 7.6.36 Address 0x7F, DEVICE_ID
-
8 Application and Implementation
- 8.1
Application Information
- 8.1.1 Conductive Objects in a Time-Varying EM Field
- 8.1.2 L-C Resonators
- 8.1.3 Multi-Channel and Single Channel Operation
- 8.1.4 Sensor Conversion Time
- 8.1.5 Sensor Current Drive Configuration
- 8.1.6 Clocking Architecture
- 8.1.7 Input Deglitch Filter
- 8.1.8 Device Status Registers
- 8.1.9 Multi-Channel Data Readback
- 8.2 Typical Application
- 8.1
Application Information
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
8.1.3 Multi-Channel and Single Channel Operation
The multi-channel package of the LDC enables the user to save board space and support flexible system design. For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant frequency of the sensor. Using a second sensor as a reference or in a differential configuration provides the capability to cancel out temperature shifts and other environmental variations. When operated in multi-channel mode, the LDC sequentially samples the selected channels - only one channel is active at any time while the other selected channels are held in an inactive state. In single channel mode, the LDC samples a single channel, which is selectable. Refer to Inactive Channel Sensor Connections for more details on inactive channels.
Inactive channels have the corresponding INAx and INBx pins tied to ground. The following table shows the registers and values that are used to configure either multi-channel or single channel modes.
Figure 53. Multi-Channel Mode Sequencing
Figure 54. Single-Channel Mode Sequencing
Table 36. Single and Multi-Channel Configuration Registers
| MODE | REGISTER | FIELD | VALUE(1) |
|---|---|---|---|
| Single channel | CONFIG, addr 0x1A | ACTIVE_CHAN [15:14] | 00 = chan 0 |
| 01 = chan 1 | |||
| 10 = chan 2 | |||
| 11 = chan 3 | |||
| MUX_CONFIG addr 0x1B | AUTOSCAN_EN [15] | 0 = continuous conversion on a single channel (default) | |
| Multi-channel | MUX_CONFIG addr 0x1B | AUTOSCAN_EN [15] | 1 = continuous conversion on multiple channels |
| MUX_CONFIG addr 0x1B | RR_SEQUENCE [14:13] | 00 = Ch0, Ch 1 | |
| 01 = Ch0, Ch 1, Ch 2 | |||
| 10 = Ch0, CH1, Ch2, Ch3 |
The digitized sensor measurement for each channel (DATAx) represents the ratio of the sensor frequency to the reference frequency.
With FREF_DIVIDERx and FIN_DIVIDERx set to 1, the sensor frequency can be calculated from:
The following table illustrates the registers that contain the fixed point sample values for each channel. The conversion result for each channel, DATAx, can be calculated with:
Table 37. LDC1612/1614 Sample Data Registers
| CHANNEL(2) | REGISTER(1) | FIELD NAME [ BITS(S) ] | VALUE(3)(4) |
|---|---|---|---|
| 0 | DATA0_MSB, addr 0x00 | DATA0 [27:16] | 12 MSBs of the 28 bit conversion for Channel 0 |
| DATA0_LSB addr 0x01 | DATA0 [15:0] | 16 LSBs of the 28 bit conversion for Channel 0 | |
| 1 | DATA1_MSB, addr 0x02 | DATA1 [27:16] | 12 MSBs of the 28 bit conversion for Channel 1 |
| DATA1_LSB, addr 0x03 | DATA1 [15:0] | 16 LSBs of the 28 bit conversion for Channel 1 | |
| 2 | DATA1_MSB, addr 0x04 | DATA2 [27:16] | 12 MSBs of the 28 bit conversion for Channel 2 |
| DATA1_LSB, addr 0x05 | DATA2 [15:0] | 16 LSBs of the 28 bit conversion for Channel 2 | |
| 3 | DATA1_MSB, addr 0x06 | DATA3 [27:16] | 12 MSBs of the 28 bit conversion for Channel 3 |
| DATA1_LSB, addr 0x07 | DATA3 [15:0] | 16 LSBs of the 28 bit conversion for Channel 0 |