ZHCSDM9A December 2014 – March 2018 LDC1612 , LDC1614
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Register List
- 7.6.2 Address 0x00, DATA0_MSB
- 7.6.3 Address 0x01, DATA0_LSB
- 7.6.4 Address 0x02, DATA1_MSB
- 7.6.5 Address 0x03, DATA1_LSB
- 7.6.6 Address 0x04, DATA2_MSB (LDC1614 only)
- 7.6.7 Address 0x05, DATA2_LSB (LDC1614 only)
- 7.6.8 Address 0x06, DATA3_MSB (LDC1614 only)
- 7.6.9 Address 0x07, DATA3_LSB (LDC1614 only)
- 7.6.10 Address 0x08, RCOUNT0
- 7.6.11 Address 0x09, RCOUNT1
- 7.6.12 Address 0x0A, RCOUNT2 (LDC1614 only)
- 7.6.13 Address 0x0B, RCOUNT3 (LDC1614 only)
- 7.6.14 Address 0x0C, OFFSET0
- 7.6.15 Address 0x0D, OFFSET1
- 7.6.16 Address 0x0E, OFFSET2 (LDC1614 only)
- 7.6.17 Address 0x0F, OFFSET3 (LDC1614 only)
- 7.6.18 Address 0x10, SETTLECOUNT0
- 7.6.19 Address 0x11, SETTLECOUNT1
- 7.6.20 Address 0x12, SETTLECOUNT2 (LDC1614 only)
- 7.6.21 Address 0x13, SETTLECOUNT3 (LDC1614 only)
- 7.6.22 Address 0x14, CLOCK_DIVIDERS0
- 7.6.23 Address 0x15, CLOCK_DIVIDERS1
- 7.6.24 Address 0x16, CLOCK_DIVIDERS2 (LDC1614 only)
- 7.6.25 Address 0x17, CLOCK_DIVIDERS3 (LDC1614 only)
- 7.6.26 Address 0x18, STATUS
- 7.6.27 Address 0x19, ERROR_CONFIG
- 7.6.28 Address 0x1A, CONFIG
- 7.6.29 Address 0x1B, MUX_CONFIG
- 7.6.30 Address 0x1C, RESET_DEV
- 7.6.31 Address 0x1E, DRIVE_CURRENT0
- 7.6.32 Address 0x1F, DRIVE_CURRENT1
- 7.6.33 Address 0x20, DRIVE_CURRENT2 (LDC1614 only)
- 7.6.34 Address 0x21, DRIVE_CURRENT3 (LDC1614 only)
- 7.6.35 Address 0x7E, MANUFACTURER_ID
- 7.6.36 Address 0x7F, DEVICE_ID
-
8 Application and Implementation
- 8.1
Application Information
- 8.1.1 Conductive Objects in a Time-Varying EM Field
- 8.1.2 L-C Resonators
- 8.1.3 Multi-Channel and Single Channel Operation
- 8.1.4 Sensor Conversion Time
- 8.1.5 Sensor Current Drive Configuration
- 8.1.6 Clocking Architecture
- 8.1.7 Input Deglitch Filter
- 8.1.8 Device Status Registers
- 8.1.9 Multi-Channel Data Readback
- 8.2 Typical Application
- 8.1
Application Information
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
6.6 Switching Characteristics - I2C
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VOLTAGE LEVELS | ||||||
| VIH | Input High Voltage | 0.7?VDD | V | |||
| VIL | Input Low Voltage | 0.3?VDD | V | |||
| VOL | Output Low Voltage (3mA sink current) | 0.4 | V | |||
| HYS | Hysteresis | 0.1?VDD | V | |||
| I2C TIMING CHARACTERISTICS | ||||||
| ƒSCL | Clock Frequency | 10 | 400 | kHz | ||
| tLOW | Clock Low Time | 1.3 | μs | |||
| tHIGH | Clock High Time | 0.6 | μs | |||
| tHD;STA | Hold Time (repeated) START condition | After this period, the first clock pulse is generated | 0.6 | μs | ||
| tSU;STA | Set-up time for a repeated START condition | 0.6 | μs | |||
| tHD;DAT | Data hold time | 0 | μs | |||
| tSU;DAT | Data setup time | 100 | ns | |||
| tSU;STO | Set-up time for STOP condition | 0.6 | μs | |||
| tBUF | Bus free time between a STOP and START condition | 1.3 | μs | |||
| tVD;DAT | Data valid time | 0.9 | μs | |||
| tVD;ACK | Data valid acknowledge time | 0.9 | μs | |||
| tSP | Pulse width of spikes that must be suppressed by the input filter(1) | 50 | ns | |||
(1) This parameter is specified by design and/or characterization and is not tested in production.
Figure 1. I2C Timing