ZHCSKG9 November 2019 LDC1001-Q1
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| POWER | |||||||
| VDD | Analog supply voltage | 4.75 | 5 | 5.25 | V | ||
| VIO | IO supply voltage | VIO ≤ VDD | 1.8 | 3.3 | 5.25 | V | |
| IDD | Supply current | Does not include the LC tank current | 1.7 | 2.3 | mA | ||
| IIO | IO supply current | Static current | 14 | µA | |||
| IDD(LP) | Low-power mode supply current | Without LC tank | 250 | µA | |||
| t(start) | Start-up time | From POR to ready-to-convert. | 2 | ms | |||
| LDC | |||||||
| fsensor_min | Minimum sensor frequency | 5 | kHz | ||||
| fsensor_max | Maximum sensor frequency | 5 | MHz | ||||
| Asensor_min | Minimum sensor amplitude | 1 | VPP | ||||
| Asensor_max | Maximum sensor amplitude | 4 | VPP | ||||
| trec | Recovery time | Oscillation start-up time after RP under-range condition | 10 | 1 / fsensor | |||
| ZRP_min | Minimum sensor RP range | 798 | Ω | ||||
| RRP_max | Maximum sensor RP range | 3.93 | MΩ | ||||
| RRP_res | RP measurement resolution | 16 | Bits | ||||
| tres(min) | Minimum response time | Minimum programmable settling time of digital filter | 192 × 1 / fsensor | s | |||
| tres(max) | Maximum response time | Maximum programmable settling time of digital filter | 6144 × 1 / fsensor | s | |||
| EXTERNAL CLOCK FOR FREQUENCY COUNTER | |||||||
| External clock frequency | 8 | MHz | |||||
| External clock input high voltage | VIO | V | |||||
| DIGITAL I/O CHARACTERISTICS | |||||||
| VIH | Logic 1 input voltage | 0.8 × VIO | V | ||||
| VIL | Logic 0 input voltage | 0.2 × VIO | V | ||||
| VOH | Logic 1 output voltage | I(SOURCE) = 400 µA | VIO– 0.3 | V | |||
| VOL | Logic 0 output voltage | I(SINK) = 400 µA | 0.3 | V | |||
| IlkgIO | Digital IO leakage current | –500 | 500 | nA | |||