ZHCSKT4B february 2020 – december 2020 ISOW7841A-Q1
PRODUCTION DATA
VCC = 5 V ±10%, SEL shorted to GND2 (over recommended operating conditions, unless otherwise specified)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VISO | Isolated supply voltage | External IISO = 0 to 50 mA | 3.13 | 3.34 | 3.56 | V |
| External IISO = 0 to 130 mA | 3 | 3.34 | 3.56 | |||
| VISO(LINE) | DC line regulation | IISO = 50 mA, VCC = 4.5 V to 5.5 V | 2 | mV/V | ||
| VISO(LOAD) | DC load regulation | IISO = 10 to 130 mA | 1% | |||
| EFF | Efficiency at maximum load current | IISO = 130 mA, CLOAD = 0.1 μF || 10
μF; VI = VSI (ISOW7841A-Q1); VI = 0 V (ISOW7841A-Q1 with F suffix) |
48% | |||
| VCC+(UVLO) | Positive-going UVLO threshold on VCC, VISO | 2.7 | V | |||
| VCC–(UVLO) | Negative-going UVLO threshold on VCC, VISO | 2.1 | V | |||
| VHYS (UVLO) | UVLO threshold hysteresis on VCC, VISO | 0.2 | V | |||
| VITH | Input pin rising threshold | 0.7 | VSI | |||
| VITL | Input pin falling threshold | 0.3 | VSI | |||
| VI(HYS) | Input pin threshold hysteresis (INx) | 0.1 | VSI | |||
| IIL | Low level input current | VIL = 0 at INx or SEL | –10 | μA | ||
| IIH | High level input current | VIH = VSI(1) at INx or SEL | 10 | μA | ||
| VOH | High level output voltage | IO = –2 mA, see Figure 8-1 | VSO(1) – 0.3 | VSO – 0.1 | V | |
| VOL | Low level output voltage | IO = 2 mA, see Figure 8-1 | 0.1 | 0.3 | V | |
| CMTI | Common mode transient immunity | VI = VSI or 0 V, VCM = 1000 V; see Figure 8-2 | 100 | kV/us | ||
| ICC_SC | DC current from supply under short circuit on VISO | VISO shorted to GND2 | 137 | mA | ||
| VISO(RIP) | Output ripple on isolated supply (pk-pk) | 20-MHz bandwidth, CLOAD = 0.1 μF || 20 μF, IISO = 130 mA | 100 | mV | ||