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ZHCSNF0B May 2018 – October 2021 ISOW1412 , ISOW1432

PRODMIX

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DFM|20
- MCSS009

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

10.7 Device Functional Modes

Table 10-1 lists the supply configuration for these devices:

Table 10-1 Supply configuration Function Table

INPUTS				OUTPUT
V_DD⁽¹⁾	V_IO	EN/FLT	MODE	V_ISOOUT⁽³⁾
< V_DD(UVLO+)	>V_IO(UVLO+)	H or Open	X	OFF
>V_DD(UVLO+)	<V_IO(UVLO+)		X	Invalid Operation
5 V	1.71 V to 5.5 V		High(shorted to V_ISOOUT)	5 V
5 V or 3.3 V	1.71 V to 5.5 V		Low(shorted to GND2) or floating ⁽²⁾	3.3 V
3.3 V	1.71 V to 5.5 V		High(shorted to V_ISOOUT)	Invalid Operation
X	X	L	X	OFF

(1) V_DD= 3.3 V, MODE shorted to V_ISOOUT(essentially V_ISOOUT = 5 V) is an invalid operation

(2) The MODE pin has a weak pulldown internally. Therefore for V_ISOOUT = 3.3 V, the MODE pin should be strongly connected to the GND2 pin in noisy system scenarios.

(3) V_ISOOUT shorted to V_ISOIN on PCB. GND2 and GISOIN pins are shorted to each other and EN=High

Table 10-2 shows the driver functional modes:

Table 10-2 Driver Functional Table

INPUTS					OUTPUTS⁽³⁾
V_DD⁽¹⁾	V_IO	EN/FLT	D	DE	Y, A	Z, B
PU	PU	H or Open	H	H	H	L
			L	H	L	H
			X	L	Hi-Z	Hi-Z
			X	Open	Hi-Z	Hi-Z
			Open	H	H	L
		L	X	X	Hi-Z	Hi-Z
PD	PU	X	X	X	Hi-Z	Hi-Z
PU	PD⁽²⁾	X	X	X	Invalid Operation

(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state

(2) A strongly driven input signal on D, DE or RE can weakly power the floating V_IO through an internal protection diode and cause an undetermined output.

(3) V_ISOOUT shorted to V_ISOIN on PCB and both GND2 pins are shorted to each other and EN=High

When the driver enable pin, DE, is logic high, the differential outputs, Y and Z, follow the logic states at data input, D. A logic high at the D input causes the Y output to go high and the Z output to go low. Therefore the differential output voltage defined by Equation 1 is positive.

Equation 1. V_OD = V_Y – V_Z

A logic low at the D input causes the Z output to go high and the Y output to go low. Therefore the differential output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when the DE pin is left open. The D pin has an internal pullup resistor. The Y output goes high and the Z output goes low when the D pin is left open while the driver enabled.

Table 10-3 shows the receiver functional modes:

Table 10-3 Receiver Functional Table

INPUTS					OUTPUT
V_DD⁽¹⁾	V_IO	EN/FLT	Differential Input V_ID = V_A- V_B	RE	R ⁽³⁾
PU	PU	H or Open	V_ID > V_IT+	L	H
			V_IT- < V_ID < V_IT+	L	Indeterminate
			V_ID < V_IT-	L	L
			X	H	Hi-Z
			X	Open	Hi-Z
			Open, Short, Idle	L	H
		L	X	X	H
PD	PU	X	X	X	Hi-Z
PU	PD⁽²⁾	H or Open	X	X	Invalid Operation
PU	PD⁽²⁾	L	X	X	Invalid Operation

(1) PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state

(2) A strongly driven input signal on D, DE or RE can weakly power the floating VIO through an internal protection diode and cause an undetermined output.

(3) V_ISOOUT shorted to V_ISOIN on PCB and both GND2 pins are shorted to each other and EN/FLT=High

The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when the differential input voltage defined by Equation 2 is greater than the positive input threshold, V_TH+.

Equation 2. V_ID = V_A – V_B

The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the negative input threshold, V_TH– . If the V_ID voltage is between the V_TH+ and V_TH– thresholds, the output is indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of V_ID are irrelevant when the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Other device feature functional states in shown in Table 10-4 and Table 10-5 below:

Table 10-4 DC-DC Converter Enable/Disable

INPUTS			OUTPUT
V_DD	V_IO	EN/FLT	V_ISOOUT
PU	PU	H or Open	3.3 V or 5 V depending on MODE pin setting
PU	PU	L	OFF

Table 10-5 General Purpose Logic Input/Output

INPUTS				OUTPUT	Comments
V_DD⁽¹⁾⁽²⁾	V_IO	EN/FLT	IN	OUT	Comments
PU	PU	H or Open	H	H	Output channel assumes logic state governed by IN
			L	L	Output channel assumes logic state governed by IN
			Open	L	Default state
		L	X	Hi-Z	Device is in disabled state when either of VDD or VIO is missing
PD	PU	X	X	Hi-Z
PU	PD	X	X	Invalid Operation

(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state

(2) V_ISOOUT shorted to V_ISOIN on PCB. GISOIN and GND2 pins are shorted to each other and EN/FLT=High