Figure 11-1 shows the recommended placement and routing of device
bypass capacitors. Below guidelines must be followed to achieve low emissions design:
- High frequency bypass capacitors 10 nF must be placed close to VDD
and VISOOUT pins, less than 1 mm distance away from device pins. This is very
essential for optimised radiated emissions performance. Ensure that these capacitors are
0402 size so that they offer least inductance (ESL).
- Bulk capacitors of atleast 10 μF must be placed on power converter
input (VDD) and output (VISOOUT) supply pins.
- Traces on VDD and GND1 must be symmetric till bypass
capacitors. Similarly traces on VISOOUT and GND2 must be symmetric.
- Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on power supply
pins, one between VISOOUT and VISOIN and the other between GND2
(11) and GISOIN(15), as shown in example PCB layout, so that any high frequency noise
from power converter output sees a high impedance before it goes to other components on
PCB.
- Do not have any metal traces or ground pour within 4 mm of power converter
output terminals VISOOUT (pin12) and GND2 (pin11). MODE pin is also in
VISOOUT domain and should be shorted to either pin 11 or pin 12 for output
voltage selection.
- Common mode choke or ferrite beads on bus terminals (Y/Z/A/B) can
minimise any high frequency noise that can couple of RS-485 bus cable which can act as
antenna and amplify that noise. This will improve Radiated emissions performance on a
system level.
- Following the layout guidelines of EVM as much as possible is highly
recommended for a low radiated emissions design. EVM Link is available in Related Documentation.