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ZHCSB73C June 2013 – July 2015 ISO7420FCC

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

D|8
- MSOI002K

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

see ⁽¹⁾

		MIN	MAX	UNIT
V_CC1, V_CC2	Supply voltage⁽²⁾	–0.5	6	V
V_IO	Voltage at INx, OUTx	–0.5	V_CC + 0.5⁽³⁾	V
I_O	Output current	–15	15	mA
T_J(Max)	Maximum junction temperature		150	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage		2.7		5.5	V
I_OH	High-level output current (V_CC ≥ 3 V)		–4			mA
I_OH	High-level output current (V_CC < 3 V)		-2			mA
I_OL	Low-level output current				4	mA
V_IH	High-level input voltage		2		5.5	V
V_IL	Low-level input voltage		0		0.8	V
t_ui	Input pulse duration	≥ 4.5-V Operation	20			ns
t_ui	Input pulse duration	< 4.5-V Operation	25			ns
1 / t_ui	Signaling rate	≥ 4.5-V Operation	0		50	Mbps
1 / t_ui	Signaling rate	< 4.5-V Operation	0		40	Mbps
T_J ⁽¹⁾	Junction temperature		–40		136	°C
T_A	Ambient temperature		-40	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see the Power Dissipation Characteristics table.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ISO7420FCC	UNIT
		D (SOIC)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	115.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	60.1	°C/W
R_θJB	Junction-to-board thermal resistance	56.4	°C/W
ψ_JT	Junction-to-top characterization parameter	17.2	°C/W
ψ_JB	Junction-to-board characterization parameter	55.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: V_CC1 and V_CC2 = 5 V ± 10%

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 12.		V_CC2 – 0.5	4.8		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 12.		V_CC2 – 0.1	5		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 12.			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 12.			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				450		mV
I_IH	High-level input current	INx = V_CC1				10	μA
I_IL	Low-level input current	INx = 0 V		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CC1 or 0 V; see Figure 14.		25	60		kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I_CC MEASUREMENT)
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CC1 or 0 V, AC Input: C_L = 15pF		0.5	1.1	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CC1 or 0 V, AC Input: C_L = 15pF		3	4.6
I_CC1		10 Mbps	C_L = 15pF		1	1.5
I_CC2		10 Mbps			4	6
I_CC1		25 Mbps			1.7	2.5
I_CC2		25 Mbps			6	8.5
I_CC1		50 Mbps			2.7	4
I_CC2		50 Mbps			8.5	12

6.6 Electrical Characteristics: V_CC1 and V_CC2 = 3.3 V ± 10%

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 12.		V_CC2 – 0.5	3		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 12.		V_CC2 – 0.1	3.3		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 12.			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 12.			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				425		mV
I_IH	High-level input current	INx = V_CC1				10	μA
I_IL	Low-level input curre	INx = 0 V		-10			μA
CMTI	Common-mode transient immunity	V_I = V_CC1 or 0 V; see Figure 14.		25	40		kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I_CC MEASUREMENT)
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CC1 or 0 V, AC Input: C_L = 15pF		0.3	0.8	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CC1 or 0 V, AC Input: C_L = 15pF		2.4	3.3
I_CC1		10 Mbps	C_L = 15pF		0.6	1.2
I_CC2		10 Mbps			3.1	4.5
I_CC1		25 Mbps			1	2
I_CC2		25 Mbps			4.2	6.1
I_CC1		40 Mbps			1.3	2.3
I_CC2		40 Mbps			5.3	7.5

6.7 Electrical Characteristics: V_CC1 and V_CC2 = 2.7 V

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –2 mA; see Figure 12.		V_CC2 – 0.3	2.5		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 12.		V_CC2 – 0.1	2.7		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 12.			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 12.			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				350		mV
I_IH	High-level input current	INx = V_CC1				10	μA
I_IL	Low-level input current	INx = 0 V		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CC1 or 0 V; see Figure 14.		25	35		kV/μs
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC I_CC MEASUREMENT)
I_CC1	Supply current for V_CC1 and V_CC2	DC to 1 Mbps	DC Input: V_I = V_CC1 or 0 V, AC Input: C_L = 15pF		0.15	0.4	mA
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CC1 or 0 V, AC Input: C_L = 15pF		2.1	3.1
I_CC1		10 Mbps	C_L = 15pF		0.4	0.7
I_CC2		10 Mbps			2.7	4
I_CC1		25 Mbps			0.7	1.2
I_CC2		25 Mbps			3.6	5
I_CC1		40 Mbps			1	1.7
I_CC2		40 Mbps			4.4	6.3

6.8 Power Dissipation Characteristics

THERMAL METRIC			ISO7420FCC	UNIT
			D (SOIC)
			8 PINS
P_D	Device power dissipation	V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF, Input a 50-Mbps 50% duty-cycle square wave	120	mW

6.9 Switching Characteristics: V_CC1 and V_CC2 = 5 V ± 10%

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 12.	10	20	37	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 12.		2.5	5	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time				2	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time				12	ns
t_r	Output signal rise time	See Figure 12.		2.5		ns
t_f	Output signal fall time	See Figure 12.		2.5		ns
t_GS	Pulse width of glitches suppressed by the input filter			12		ns
t_fs	Fail-safe output delay time from input data or power loss	See Figure 13.		8		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.10 Switching Characteristics: V_CC1 and V_CC2 = 3.3 V ± 10%

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 12.	10	22	40	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 12.			3	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time				2	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time				19	ns
t_r	Output signal rise time	See Figure 12.		3		ns
t_f	Output signal fall time			3		ns
t_GS	Pulse width of glithes suppressed by the input filter			12.5		ns
t_fs	Fail-safe output delay time from input power loss	See Figure 13.		8		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

6.11 Switching Characteristics: V_CC1 and V_CC2 = 2.7 V

T_A = –40°C to 125°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 12.	15	26	45	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 12.			3	ns
t_sk(o) ⁽²⁾	Channel-to-channel output skew time				2	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time				22	ns
t_r	Output signal rise time	See Figure 12.		3		ns
t_f	Output signal fall time	See Figure 12.		3		ns
t_GS	Pulse width of glitches suppressed by the input filter			13.5		ns
t_fs	Fail-safe output delay time from input power loss	See Figure 13.		8		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.