ZHCSB73C June 2013 – July 2015 ISO7420FCC
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: VCC1 and VCC2 = 5 V ± 10%
- 6.6 Electrical Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
- 6.7 Electrical Characteristics: VCC1 and VCC2 = 2.7 V
- 6.8 Power Dissipation Characteristics
- 6.9 Switching Characteristics: VCC1 and VCC2 = 5 V ± 10%
- 6.10 Switching Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
- 6.11 Switching Characteristics: VCC1 and VCC2 = 2.7 V
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Specifications
6.1 Absolute Maximum Ratings
see (1)| MIN | MAX | UNIT | |||||
|---|---|---|---|---|---|---|---|
| VCC1, VCC2 | Supply voltage(2) | –0.5 | 6 | V | |||
| VIO | Voltage at INx, OUTx | –0.5 | VCC + 0.5(3) | V | |||
| IO | Output current | –15 | 15 | mA | |||
| TJ(Max) | Maximum junction temperature | 150 | °C | ||||
| Tstg | Storage temperature | –65 | 150 | °C | |||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VCC1, VCC2 | Supply voltage | 2.7 | 5.5 | V | ||
| IOH | High-level output current (VCC ≥ 3 V) | –4 | mA | |||
| High-level output current (VCC < 3 V) | -2 | mA | ||||
| IOL | Low-level output current | 4 | mA | |||
| VIH | High-level input voltage | 2 | 5.5 | V | ||
| VIL | Low-level input voltage | 0 | 0.8 | V | ||
| tui | Input pulse duration | ≥ 4.5-V Operation | 20 | ns | ||
| < 4.5-V Operation | 25 | |||||
| 1 / tui | Signaling rate | ≥ 4.5-V Operation | 0 | 50 | Mbps | |
| < 4.5-V Operation | 0 | 40 | ||||
| TJ (1) | Junction temperature | –40 | 136 | °C | ||
| TA | Ambient temperature | -40 | 25 | 125 | °C | |
(1) To maintain the recommended operating conditions for TJ, see the Power Dissipation Characteristics table.
6.4 Thermal Information
| THERMAL METRIC(1) | ISO7420FCC | UNIT | ||
|---|---|---|---|---|
| D (SOIC) | ||||
| 8 PINS | ||||
| RθJA | Junction-to-ambient thermal resistance | 115.1 | °C/W | |
| RθJC(top) | Junction-to-case (top) thermal resistance | 60.1 | °C/W | |
| RθJB | Junction-to-board thermal resistance | 56.4 | °C/W | |
| ψJT | Junction-to-top characterization parameter | 17.2 | °C/W | |
| ψJB | Junction-to-board characterization parameter | 55.8 | °C/W | |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics: VCC1 and VCC2 = 5 V ± 10%
TA = –40°C to 125°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VOH | High-level output voltage | IOH = –4 mA; see Figure 12. | VCC2 – 0.5 | 4.8 | V | ||
| IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 5 | |||||
| VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
| IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
| VI(HYS) | Input threshold voltage hysteresis | 450 | mV | ||||
| IIH | High-level input current | INx = VCC1 | 10 | μA | |||
| IIL | Low-level input current | INx = 0 V | –10 | μA | |||
| CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 60 | kV/μs | ||
| SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
| ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.5 | 1.1 | mA | |
| ICC2 | 3 | 4.6 | |||||
| ICC1 | 10 Mbps | CL = 15pF | 1 | 1.5 | |||
| ICC2 | 4 | 6 | |||||
| ICC1 | 25 Mbps | 1.7 | 2.5 | ||||
| ICC2 | 6 | 8.5 | |||||
| ICC1 | 50 Mbps | 2.7 | 4 | ||||
| ICC2 | 8.5 | 12 | |||||
6.6 Electrical Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
TA = –40°C to 125°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VOH | High-level output voltage | IOH = –4 mA; see Figure 12. | VCC2 – 0.5 | 3 | V | ||
| IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 3.3 | |||||
| VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
| IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
| VI(HYS) | Input threshold voltage hysteresis | 425 | mV | ||||
| IIH | High-level input current | INx = VCC1 | 10 | μA | |||
| IIL | Low-level input curre | INx = 0 V | -10 | μA | |||
| CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 40 | kV/μs | ||
| SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
| ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.3 | 0.8 | mA | |
| ICC2 | 2.4 | 3.3 | |||||
| ICC1 | 10 Mbps | CL = 15pF | 0.6 | 1.2 | |||
| ICC2 | 3.1 | 4.5 | |||||
| ICC1 | 25 Mbps | 1 | 2 | ||||
| ICC2 | 4.2 | 6.1 | |||||
| ICC1 | 40 Mbps | 1.3 | 2.3 | ||||
| ICC2 | 5.3 | 7.5 | |||||
6.7 Electrical Characteristics: VCC1 and VCC2 = 2.7 V
TA = –40°C to 125°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VOH | High-level output voltage | IOH = –2 mA; see Figure 12. | VCC2 – 0.3 | 2.5 | V | ||
| IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 2.7 | |||||
| VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
| IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
| VI(HYS) | Input threshold voltage hysteresis | 350 | mV | ||||
| IIH | High-level input current | INx = VCC1 | 10 | μA | |||
| IIL | Low-level input current | INx = 0 V | –10 | μA | |||
| CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 35 | kV/μs | ||
| SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
| ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.15 | 0.4 | mA | |
| ICC2 | 2.1 | 3.1 | |||||
| ICC1 | 10 Mbps | CL = 15pF | 0.4 | 0.7 | |||
| ICC2 | 2.7 | 4 | |||||
| ICC1 | 25 Mbps | 0.7 | 1.2 | ||||
| ICC2 | 3.6 | 5 | |||||
| ICC1 | 40 Mbps | 1 | 1.7 | ||||
| ICC2 | 4.4 | 6.3 | |||||
6.8 Power Dissipation Characteristics
| THERMAL METRIC | ISO7420FCC | UNIT | ||
|---|---|---|---|---|
| D (SOIC) | ||||
| 8 PINS | ||||
| PD | Device power dissipation | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50-Mbps 50% duty-cycle square wave |
120 | mW |
6.9 Switching Characteristics: VCC1 and VCC2 = 5 V ± 10%
TA = –40°C to 125°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tPLH, tPHL | Propagation delay time | See Figure 12. | 10 | 20 | 37 | ns |
| PWD(1) | Pulse width distortion |tPHL – tPLH| | 2.5 | 5 | ns | ||
| tsk(o) (2) | Channel-to-channel output skew time | 2 | ns | |||
| tsk(pp) (3) | Part-to-part skew time | 12 | ns | |||
| tr | Output signal rise time | See Figure 12. | 2.5 | ns | ||
| tf | Output signal fall time | 2.5 | ns | |||
| tGS | Pulse width of glitches suppressed by the input filter | 12 | ns | |||
| tfs | Fail-safe output delay time from input data or power loss | See Figure 13. | 8 | μs | ||
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
6.10 Switching Characteristics: VCC1 and VCC2 = 3.3 V ± 10%
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tPLH, tPHL | Propagation delay time | See Figure 12. | 10 | 22 | 40 | ns |
| PWD(1) | Pulse width distortion |tPHL – tPLH| | 3 | ns | |||
| tsk(o) (2) | Channel-to-channel output skew time | 2 | ns | |||
| tsk(pp) (3) | Part-to-part skew time | 19 | ns | |||
| tr | Output signal rise time | See Figure 12. | 3 | ns | ||
| tf | Output signal fall time | 3 | ns | |||
| tGS | Pulse width of glithes suppressed by the input filter | 12.5 | ns | |||
| tfs | Fail-safe output delay time from input power loss | See Figure 13. | 8 | μs | ||
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics: VCC1 and VCC2 = 2.7 V
TA = –40°C to 125°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tPLH, tPHL | Propagation delay time | See Figure 12. | 15 | 26 | 45 | ns |
| PWD(1) | Pulse width distortion |tPHL – tPLH| | 3 | ns | |||
| tsk(o) (2) | Channel-to-channel output skew time | 2 | ns | |||
| tsk(pp) (3) | Part-to-part skew time | 22 | ns | |||
| tr | Output signal rise time | See Figure 12. | 3 | ns | ||
| tf | Output signal fall time | 3 | ns | |||
| tGS | Pulse width of glitches suppressed by the input filter | 13.5 | ns | |||
| tfs | Fail-safe output delay time from input power loss | See Figure 13. | 8 | μs | ||
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
6.12 Typical Characteristics
Figure 1. Supply Current Per Channel vs Data Rate
Figure 5. VCC1 and VCC2 Undervoltage Threshold vs Free-Air Temperature
Figure 7. Output Jitter vs Data Rate
Figure 2. Supply Current for Both Channels vs Data Rate
Figure 4. Low-Level Output Voltage vs Low-Level Output Current
Figure 6. Propagation Delay Time vs Free-Air Temperature
Figure 8. Input Glitch Suppression Time vs Free-Air Temperature
Figure 9. Eye Diagram at 50 Mbps, 5V at 25°C
Figure 11. Eye Diagram at 40 Mbps, 2.7V at 25°C
Figure 10. Eye Diagram at 40 Mbps, 3.3V at 25°C