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ZHCSDT1D june 2015 – may 2023 ISO5451

PRODUCTION DATA

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DW|16

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOLTAGE SUPPLY
V_IT+(UVLO1)	Positive-going UVLO1 threshold voltage input side (V_CC1 – GND1)				2.25	V
V_IT-(UVLO1)	Negative-going UVLO1 threshold voltage input side (V_CC1 – GND1)		1.7			V
V_HYS(UVLO1)	UVLO1 Hysteresis voltage (V_IT+ – V_IT–) input side			0.24		V
V_IT+(UVLO2)	Positive-going UVLO2 threshold voltage output side (V_CC2 – GND2)			12	13	V
V_IT-(UVLO2)	Negative-going UVLO2 threshold voltage output side (V_CC2 – GND2)		9.5	11		V
V_HYS(UVLO2)	UVLO2 Hysteresis voltage (V_IT+ – V_IT–) output side			1		V
I_Q1	Input supply quiescent current			2.8	4.5	mA
I_Q2	Output supply quiescent current			3.6	6	mA
LOGIC I/O
V_IT+(IN, RST)	Positive-going input threshold voltage (IN+, IN–, RST)				0.7 × V_CC1	V
V_IT-(IN, RST)	Negative-going input threshold voltage (IN+, IN–, RST)		0.3 × V_CC1			V
V_HYS(IN, RST)	Input hysteresis voltage (IN+, IN–, RST)			0.15 × V_CC1		V
I_IH	High-level input leakage at (IN+) ⁽¹⁾	IN+ = V_CC1		100		μA
I_IL	Low-level input leakage at (IN–, RST) ⁽²⁾	IN– = GND1, RST = GND1		–100		μA
I_PU	Pull-up current of FLT, RDY	V_(RDY) = GND1, V_(FLT) = GND1		100		μA
V_OL	Low-level output voltage at FLT, RDY	I_(FLT) = 5 mA			0.2	V
GATE DRIVER STAGE
V_(OUTPD)	Active output pulldown voltage	I_OUT = 200 mA, V_CC2 = open			2	V
V_(OUTH)	High-level output voltage	I_OUT = –20 mA	V_CC2 – 0.5	V_CC2 – 0.24		V
V_(OUTL)	Low-level output voltage	I_OUT = 20 mA		V_EE2 + 13	V_EE2 + 50	mV
I_(OUTH)	High-level output peak current	IN+ = high, IN– = low, V_OUT = V_CC2 - 15 V	1.5	2.5		A
I_(OUTL)	Low-level output peak current	IN+ = low, IN– = high, V_OUT = V_EE2 + 15 V	3.4	5		A
ACTIVE MILLER CLAMP
V_(CLP)	Low-level clamp voltage	I_(CLP) = 20 mA		V_EE2 + 0.015	V_EE2 + 0.08	V
I_(CLP)	Low-level clamp current	V_(CLAMP) = V_EE2 + 2.5 V	1.6	2.5		A
V_(CLTH)	Clamp threshold voltage		1.6	2.1	2.5	V
SHORT CIRCUIT CLAMPING
V_{(CLP_OUT)}	Clamping voltage (V_OUT - V_CC2)	IN+ = high, IN– = low, t_CLP=10 μs, I_(OUTH) = 500 mA		0.8	1.3	V
V_{(CLP_CLAMP)}	Clamping voltage (V_CLP - V_CC2)	IN+ = high, IN– = low, t_CLP=10 μs, I_(CLP) = 500 mA		1.3		V
V_{(CLP_CLAMP)}	Clamping voltage at CLAMP	IN+ = High, IN– = Low, I_(CLP) = 20 mA		0.7	1.1	V
DESAT PROTECTION
I_(CHG)	Blanking capacitor charge current	V_(DESAT) - GND2 = 2 V	0.42	0.5	0.58	mA
I_(DCHG)	Blanking capacitor discharge current	V_(DESAT) - GND2 = 6 V	9	14		mA
V_(DSTH)	DESAT threshold voltage with respect to GND2		8.3	9	9.5	V
V_(DSL)	DESAT voltage with respect to GND2, when OUT is driven low		0.4		1	V

(1) I_IH for IN–, RST pin is zero as they are pulled high internally.

(2) I_IL for IN+ is zero, as it is pulled low internally.