ZHCSGU8E June 2017 – August 2018 ISO1211 , ISO1212
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The board layout for ISO1211 and ISO1212 can be completed in two layers. On the field side, place RSENSE, CIN, and RTHR on the top layer. Use the bottom layer as the field ground (FGND) plane. TI recommends using RSENSE and CIN in 0603 footprint for a compact layout, although larger sizes (0805) can also be used. The CIN capacitor is a 50-V capacitor and is available in the 0603 footprint. Keep CIN as close to the ISO121x device as possible. The SUB pin on the ISO1211 device and the SUB1 and SUB2 pins on the ISO1212 device should be left unconnected. For group isolated design, use vias to connect the FGND pins of the ISO121x device to the bottom FGND plane. The placement of the RTHR resistor is flexible, although the resistor pin connected to external high voltage should not be placed within 4 mm of the ISO121x device pins or the CIN and RSENSE pins to avoid flashover during EMC tests.
Only a decoupling capacitor is required on side 1. Place this capacitor on the top-layer, with the bottom layer for GND1.
If a board with more than two layers is used, placing two ISO121x devices on the top-and bottom layers (back-to-back) is possible to achieve a more compact board. The inner layers can be used for FGND.
Figure 31 and Figure 32 show the example layouts.
In some designs, placing the LED on the field side is desirable although it is powered from VCC1. In such cases, the signal carrying current to the LED can be routed in an inner layer without compromising the isolation of the digital-input module as shown in Figure 33. The LED must be placed with at least 4-mm spacing between other components and connections on side 1 to ensure adequate isolation.