ZHCSL04A March 2020 – July 2020 ISO1044
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| DEVICE SWITCHING CHARACTERISTICS | ||||||
| tPROP(LOOP1) | Total loop delay, driver input TXD to receiver RXD, recessive to dominant | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V | 150 | 203 | ns | |
| See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V | 150 | 199 | ns | |||
| tPROP(LOOP2) | Total loop delay, driver input TXD to receiver RXD, dominant to recessive | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V | 175 | 219 | ns | |
| See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V | 175 | 212 | ns | |||
| tUV_RE_ENABLE | Re-enable time after Undervoltage event | Time for device to return to normal operation from VCC1 or VCC2 under voltage event | 300.0 | μs | ||
| CMTI | Common mode transient immunity | TXD=VCC1 or GND1, VCM = 1200VPK , See Figure 7-9 | 85 | kV/μs | ||
| DRIVER SWITCHING CHARACTERISTICS | ||||||
| tpHR | Propagation delay time, Low-to-High TXD edge to driver recessive | See Figure 7-3 , RL = 60 Ω and CL = 100 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 85 | 105 | ns | |
| tpLD | Propagation delay time, High-to-Low TXD edge to driver dominant | 70 | 105 | |||
| tsk(p) | pulse skew (|tpHR - tpLD|) | 12.5 | ||||
| tR | Differential output signal rise time | 27 | ||||
| tF | Differential output signal fall time | 42 | ||||
| VSYM | Driver symmetry (VO(CANH) + VO(CANL))/VCC | See Figure 7-3 and Figure 9-3 , RTERM =60 Ω, CL =open, CSPLIT= 4.7nF, TXD= Dominant or receissive or toggling at 250 kHz, 1 MHz | 0.9 | 1.1 | V/V | |
| tTXD_DTO | Dominant time out | See Figure 7-7 , RL = 60 Ω and CL = open | 1.2 | 3.8 | ms | |
| RECEIVER SWITCHING CHARACTERISTICS | ||||||
| tpRH | Propagation delay time, bus dominant-to-recessive input edge to RXD high output | See Figure 7-5 , CL(RXD) = 15 pF, | 90 | 130 | ns | |
| tpDL | Propogation delay time, bus recessive-to-dominant input edge to RXD low output | 71 | 110 | ns | ||
| tR | Output signal rise time(RXD) | 1 | ns | |||
| tF | Output signal fall time(RXD) | 1 | ns | |||
| FD TIMING PARAMETERS | ||||||
| tBIT(BUS) | Bit time on CAN bus output pins with tBIT(TXD) = 500 ns | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 435.0 | 530.0 | ns | |
| Bit time on CAN bus output pins with tBIT(TXD) = 200 ns | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 155.0 | 210.0 | ns | ||
| tBIT(RXD) | Bit time on RXD output pin with tBIT(TXD) = 500 ns | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 400 | 550.0 | ns | |
| Bit time on RXD output pin with tBIT(TXD) = 200 ns | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns | 120.0 | 220.0 | ns | ||
| ?tREC | Receiver timing symmetry with tBIT(TXD) = 500 ns | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) | -65.0 | 40.0 | ns | |
| Receiver timing symmetry with tBIT(TXD) = 200 ns | See Figure 7-6 , RL = 60 ?, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) | -45.0 | 15.0 | ns | ||