ZHCSEP9C december 2015 – december 2020 HD3SS214
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings #GUID-AEF84F8B-5035-497D-BF42-BEE5DCF32E24/SLAS9018663 #GUID-AEF84F8B-5035-497D-BF42-BEE5DCF32E24/SLAS9012713
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Electrical Characteristics, Device Parameters
- 6.7 Timing Requirements
- 6.8 Typical Characteristics
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
Figure 5-1 ZXH
Package50-ball (nFBGA)Top ViewPin Functions
| PIN | I/O | DESCRIPTION(1) | |
|---|---|---|---|
| NO. | NAME | ||
| A1 | Dx_SEL | Control I | High Speed Port Selection Control Pins |
| A2,J4 | VDD | Supply | 3.3 V Positive power supply voltage |
| A4 | DA0(n) | I/O | Port A, Channel 0, High Speed Negative Signal |
| A5 | DA1(n) | I/O | Port A, Channel 1, High Speed Negative Signal |
| A6 | DA2(n) | I/O | Port A, Channel 2, High Speed Negative Signal |
| A8 | DA3(p) | I/O | Port A, Channel 3, High Speed Positive Signal |
| A9 | DA3(n) | I/O | Port A, Channel 3, High Speed Negative Signal |
| B1 | DC0(n) | I/O | Port C, Channel 0, High Speed Negative Signal |
| B2 | DC0(p) | I/O | Port C, Channel 0, High Speed Positive Signal |
| B3,C8,G2,G8,H4,H7 | GND | Supply | Ground |
| B4 | DA0(p) | I/O | Port A, Channel 0, High Speed Positive Signal |
| B5 | DA1(p) | I/O | Port A, Channel 1, High Speed Positive Signal |
| B6 | DA2(p) | I/O | Port A, Channel 2, High Speed Positive Signal |
| B7 | OE | I | Output Enable: OE = VIH: Normal Operation OE = VIL: Standby Mode |
| B8 | DB0(p) | I/O | Port B, Channel 0, High Speed Positive Signal |
| B9 | DB0(n) | I/O | Port B, Channel 0, High Speed Negative Signal |
| C2 | AUX_SEL | Control I | AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin |
| D1 | DC1(n) | I/O | Port C, Channel 1, High Speed Negative Signal |
| D2 | DC1(p) | I/O | Port C, Channel 1, High Speed Positive Signal |
| D8 | DB1(p) | I/O | Port B, Channel 1, High Speed Positive Signal |
| D9 | DB1(n) | I/O | Port B, Channel 1, High Speed Negative Signal |
| E1 | DC2(n) | I/O | Port C, Channel 2, High Speed Negative Signal |
| E2 | DC2(p) | I/O | Port C, Channel 2, High Speed Positive Signal |
| E8 | DB2(p) | I/O | Port B, Channel 2, High Speed Positive Signal |
| E9 | DB2(n) | I/O | Port B, Channel 2, High Speed Negative Signal |
| F1 | DC3(n) | I/O | Port C, Channel 3, High Speed Negative Signal |
| F2 | DC3(p) | I/O | Port C, Channel 3, High Speed Positive Signal |
| F8 | DB3(p) | I/O | Port B, Channel 3, High Speed Positive Signal |
| F9 | DB3(n) | I/O | Port B, Channel 3, High Speed Negative Signal |
| H1 | AUXC(n) | I/O | Port C AUX Negative Signal |
| H2 | AUXC(p) | I/O | Port C AUX Positive Signal |
| H3 | HPDB | I/O | Port B Hot Plug Detect |
| H6 | AUXB(p) | I/O | Port B AUX Positive Signal |
| H5 | DDCCLK_B | I/O | Port B DDC Clock Signal |
| H8 | DDCCLK_A | I/O | Port A DDC Clock Signal |
| H9 | AUXA(p) | I/O | Port A AUX Positive Signal |
| J1 | HPDC | I/O | Port C Hot Plug Detect |
| J2 | HPDA | I/O | Port A Hot Plug Detect |
| J3 | DDCCLK_C | I/O | Port C DDC Clock Signal |
| J5 | DDCDAT_B | I/O | Port B DDC Data Signal |
| J6 | AUXB(n) | I/O | Port B AUX Negative Signal |
| J7 | DDCDAT_C | I/O | Port C DDC Data Signal |
| J8 | DDCDAT_A | I/O | Port A DDC Data Signal |
| J9 | AUXA(n) | I/O | Port A AUX Negative Signal |
(1) The high speed data ports incorporate 20-kΩ pull down resistors
that are switched in when a port is not selected and switched out when the port
is selected.