The following guidelines must be followed when designing the layout:
- Decoupling capacitors must be placed as close to the VDD1/VDD2 pins as
possible.
- The die attach pad (DAP) must have a low-impedance connection to the nearest
GND plane. This is typically accomplished with vias connecting the surface
GND plane to inner-layer GND planes. One recommended option is to place 14
vias spaced ≥1.0 mm apart in a seven by two grid as shown in Figure 11-1.
- When placing the FPC402 underneath an SFP or QSFP cage, on the opposite side
of the PCB, as shown in Figure 11-1, take note of the SFP/QSFP keep-out areas as well as any keep-out area
required for the pressfit assembly tooling.
- Pin 32 (CAPL) must have a low-impedance, low-inductance path to a 2.2-μF
decoupling capacitor to GND. If space constraints force this capacitor to be
placed away from the pin, then a wider metal trace (that is, 20 mil) to the
capacitor, using an inner layer if necessary, is recommended.
- A GND pin is provided (pin 27) to make it easy to probe GND near the FPC402,
especially in applications where the opposite side of the PCB is covered by
an SFP or QSFP cage and therefore inaccessible. To maximize the benefit of
this probe point, connect this pin to the local GND plane (that is, to the
DAP and associated GND vias) through a low-impedance trace. In addition, it
may be helpful to route a short trace to a probe point for easy access.