ZHCSLX3C June 2017 – September 2020 FPC402
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Host-Side Control Interface
- 8.3.2 LED Control
- 8.3.3 Low-Speed Output Signal Control
- 8.3.4 Low-Speed Input Status and Interrupt Generation
- 8.3.5 Downstream (Port-Side) I2C Master
- 8.3.6 Data Prefetch From Modules
- 8.3.7 Scheduled Write
- 8.3.8 Protocol Timeouts
- 8.3.9 General-Purpose Inputs and Outputs
- 8.3.10 Hot-Plug Support
- 8.4 Device Functional Modes
- 8.5 Programming
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.2 SPI Host-Side Control Interface
If SPI is used as the host-side communication protocol, the maximum number of FPC402 devices which can share a single SPI bus is technically unlimited. The read and write latency from/to the downstream ports will increase as the length of the SPI chain increases.
SPI does not require each FPC402 to have an address. The FPC402 devices are connected in a daisy-chain fashion as shown in Figure 8-6. The first FPC402 will connect CTRL3 (MOSI) to the MOSI signal of the host controller. CTRL4 (MISO) on the first FPC402 will connect to the subsequent CTRL3 (MOSI) signal of another FPC402, and continues until the final CTRL4 (MISO) signal connects back to the MISO signal of the host controller. All FPC402 devices will connect CTRL1 (SCK) and CTRL2 (SS_N) to the same SCK and SS_N pin on the host controller. For LED blink synchronization across multiple FPC402 devices, the SPI_LED_SYNC pin must be connected across all FPC402 devices in SPI mode. This is not necessary in I2C mode.
Each FPC402 device in the SPI chain will capture and act upon the command in its shift register when SS_N transitions from low (0) to high (1). The MOSI input is ignored and the MISO output is high impedance whenever SS_N is deasserted high.
The prior SPI command, address, and data are shifted out on MISO as the current SPI command, address, and data are shifted in on MOSI. In all SPI transactions, the MISO output signal is enabled asynchronously whenever SS_N is asserted low.
Figure 8-6 FPC402 Connection Diagram for SPI ModeThe SPI address space for FPC402 applications is designed such that each port being controlled and each logical device address within each port is accessible to the host controller through a unique 12-bit address. Refer to Table 8-7 for the appropriate address offset mapping.
For a system with up to N FPC402 devices on a single SPI chain, the full SPI address map is as follows.
| FPC402 INSTANCE NUMBER | ADDRESS RANGE | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| PORT 0 | PORT 1 | PORT 2 | PORT 3 | FPC402 REGS | |||||
| DEVICE 0 DEFAULT = 0xA0(1) | DEVICE 1 DEFAULT = 0xA2(1) | DEVICE 0 DEFAULT = 0xA0(1) | DEVICE 1 DEFAULT = 0xA2(1) | DEVICE 0 DEFAULT = 0xA0(1) | DEVICE 1 DEFAULT = 0xA2(1) | DEVICE 0 DEFAULT = 0xA0(1) | DEVICE 1 DEFAULT = 0xA2(1) | ||
| 0 | 0x000 to 0x0FF | 0x100 to 0x1FF | 0x200 to 0x2FF | 0x300 to 0x3FF | 0x400 to 0x4FF | 0x500 to 0x5FF | 0x600 to 0x6FF | 0x700 to 0x7FF | 0x800 to 0x8FF |
| 1 | |||||||||
| 2 | |||||||||
| – | |||||||||
| N | |||||||||
In SPI mode, the CTRL4 pin has a driver impedance of 60 Ω (typical). To minimize ringing due to the fast edge rate of the driver, TI recommends matching the transmission line characteristic impedance with the driver impedance. A series resistor near the driver pin (CTRL4) may be used to facilitate this impedance matching. If ringing is a concern, the IBIS model provided may be used for simulations.