The FPC202 has six general-purpose inputs per port which can be used to monitor the low-speed outputs from the module. The host controller can monitor the status of these signals for each port by reading the appropriate registers in the FPC202. In addition, the FPC202 can be configured to generate an interrupt to the host through the HOST_INT_N signal whenever one or more of the low-speed input signals change state. The interrupt can be configured to trigger on the falling edge, the rising edge, or both the falling and rising edges. A single register stores flags for which inputs and edges are responsible for the trigger.

The recommended signal connection is as follows. S0_IN_A, S0_IN_B, S0_IN_C, S1_IN_A, S1_IN_B, and S1_IN_C are not restricted to this port pin assignment, and in fact they can be used to monitor the status of any low-speed 3.3-V signal required for the application.

The events which trigger an active-low interrupt on the HOST_INT_N pin are user-configurable. Multiple FPC202s’ HOST_INT_N pins can be connected together in a wired-or fashion. Interrupt generation can be configured as follows:

The FPC202 is also able to generate an interrupt based on pre-fetched data. This is known as a data-driven interrupt. The FPC202 monitors up to four bytes within the pre-fetched range for each port. For each of the bytes, the register offset address is programmed to a local FPC202 register as well as the enable bit fields which will trigger the interrupt. When one of the enabled bits of the four monitored bytes changes state from a '0' to a '1' and stays a '1' for two consecutive periodic pre-fetch cycles (0→1→1), the interrupt is generated and the periodic pre-fetch operation is halted. The FPC202 has four registers per port, which contain the sampled data from the bytes being monitored after the interrupt is triggered. To clear the interrupt, the trigger source byte's sampled data register is read. The periodic pre-fetch must be restarted after the interrupt is cleared with an I2C command. Because it takes two periodic pre-fetch cycles to trigger this interrupt, it may take up to 10 ms for the host to see the trigger after the downstream module's monitored bit field changes for the fastest periodic pre-fetch setting.

The FPC202 also has the ability to generate an interrupt if there is a mishap in the downstream I2C bus. The SDA bus and the SCL bus each have timers that will trigger an interrupt if they are held in a low state too long due to excessive clock stretching or a port error. Once the interrupt is triggered, it is cleared by issuing a port reset on the relevant port. These interrupts are known as SCL Stuck and SDA Stuck interrupts and can be configured individually for each port. By default, the SCL Stuck interrupt will trigger after the SCL bus is held low for 35 ms (typical). This value is configurable individually by port. The SDA Stuck interrupt will trigger after the SDA is held low for 1 s (typical). The user may issue a port reset sequence (9 consecutive SCL clock cycles with the last being an I2C stop condition) or module reset to restore the module to a known state.

When a host-side interrupt is triggered, the host must determine the source and cause of the interrupt. The recommended procedure for identifying the source and cause of an interrupt is as follows:

1. Read the FPC202 aggregated port interrupt flags of the first FPC202 instance to see which, if any, downstream port triggered the interrupt.
2. If this instance of the FPC202 has any aggregated port interrupts flagged, read all of the status registers to determine the source of the interrupt and clear it. If an SCL Stuck or SDA Stuck interrupt is triggered, a port reset must be issued and the periodic pre-fetch must be restarted. The host may also perform other housekeeping activities based on the interrupt, such as change the state of the LEDs after a module is no longer present.
3. Repeat steps 1 and 2 for the next FPC202 instance, until the HOST_INT_N bus is cleared.

This procedure applies to every FPC202 device which is wire-or’ed to the host-side interrupt signal. The total time required for the host to identify the source and cause of the interrupt for an implementation consisting of N total FPC202’s, where all N HOST_INT_N outputs are wire-or’ed together, is as follows:

T_interrupt = Delay between the IN_* pin changing state and the corresponding FPC202 device triggering an interrupt (50 μs max).

T_read = Time required to read a single register from N FPC202 devices.

For I2C mode, T_read = (9*4*N)/F_I2C, where F_I2C is the SCL clock frequency.

For SPI mode, T_read = (29*2*N)/F_SPI + T_OFF-SSN, where F_SPI is the SCK clock frequency, and T_OFF-SSN is the SS_N off time.

T_total = T_interrupt + 4*T_read

Table 7-4 gives some examples of T_total for different I2C/SPI frequencies and different values of N.

Request access to the FPC202 Programmer's Guide (SNLU229) here for more details on how to configure the interrupts.