| 0 |
0x00 |
I2C Device ID |
7:1 |
RW |
IDx |
Device ID
Port0/Port1 |
7-bit address of Serializer.
Defaults to address configured by the IDx strap pin.
If PORT1_I2C_EN is set, this value defaults to the IDx strap value + 1 for Port1.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 0 |
RW |
ID Setting |
I2C ID setting.
0: Device I2C address is from IDx pin (default).
1: Device I2C address is from 0x00[7:1]. |
| 1 |
0x01 |
Reset |
7:2 |
|
0x00 |
|
Reserved. |
| 1 |
RW |
Digital RESET1 |
Reset the entire digital block including registers. This bit is self-clearing.
0: Normal operation (default).
1: Reset. |
| 0 |
RW |
Digital RESET0 |
Reset the entire digital block except registers. This bit is self-clearing.
0: Normal operation (default).
1: Reset.
Registers which are loaded by pin strap will be restored to their original strap value when this bit is set. These registers show 'Strap' as their default value in this table.
Registers 0x18, 0x19, 0x1A, and 0x48-0x55 are also restored to their default value when this bit is set. |
| 3 |
0x03 |
General Configuration |
7 |
RW |
0xD2 |
Back channel CRC Checker Enable |
Enable/disable back channel CRC Checker.
0: Disable.
1: Enable (default). |
| 6 |
|
|
Reserved. |
| 5 |
RW |
I2C Remote Write Auto Acknowledge
Port0/Port1 |
Automatically acknowledge I2C remote writes. When enabled, I2C writes to the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the Deserializer to acknowledge the write. This allows higher throughput on the I2C bus. Note: this mode will prevent any NACK from a remote device from reaching the I2C master.
0: Disable (default).
1: Enable.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 4 |
RW |
Filter Enable |
HS, VS, DE two-clock filter. When enabled, pulses less than two full PCLK cycles on the DE, HS, and VS inputs will be rejected.
0: Filtering disable.
1: Filtering enable (default). |
| 3 |
RW |
I2C Pass-through
Port0/Port1 |
I2C pass-through mode. Read/Write transactions matching any entry in the Slave Alias registers will be passed through to the remote Deserializer.
0: Pass-through disabled (default).
1: Pass-through enabled.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 2 |
|
|
Reserved. |
| 1 |
RW |
PCLK Auto |
Switch over to internal oscillator in the absence of PCLK.
0: Disable auto-switch.
1: Enable auto-switch (default). |
| 0 |
|
|
Reserved. |
| 4 |
0x04 |
Mode Select |
7 |
RW |
0x80 |
Failsafe State |
Input failsafe state.
0: Failsafe to High.
1: Failsafe to Low (default). |
| 6 |
|
|
Reserved. |
| 5 |
RW |
CRC Error Reset |
Clear back channel CRC Error counters. This bit is NOT self-clearing.
0: Normal operation (default).
1: Clear counters. |
| 4 |
|
|
Reserved. |
| 3:0 |
|
|
|
Reserved. |
| 5 |
0x05 |
I2C Control |
7:5 |
|
0x00 |
|
Reserved. |
| 4:3 |
RW |
SDA Output Delay |
Configures output delay on the SDA output. Setting this value will increase output delay in units of 40ns.
Nominal output delay values for SCL to SDA are:
00: 240ns (default).
01: 280ns.
10: 320ns.
11: 360ns. |
| 2 |
RW |
Local Write Disable |
Disable remote writes to local registers. Setting this bit to 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Serializer registers from an I2C master attached to the Deserializer. Setting this bit does not affect remote access to I2C slaves at the Serializer.
0: Enable (default).
1: Disable. |
| 1 |
RW |
I2C Bus Timer Speedup |
Speed up I2C bus Watchdog Timer.
0: Watchdog Timer expires after approximately 1s (default).
1: Watchdog Timer expires after approximately 50µs. |
| 0 |
RW |
I2C Bus Timer Disable |
Disable I2C bus Watchdog Timer. The I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1s, the I2C bus will be assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL.
0: Enable (default).
1: Disable. |
| 6 |
0x06 |
DES ID |
7:1 |
RW |
0x00 |
DES Device ID
Port0/Port1 |
7-bit I2C address of the remote Deserializer. A value of 0 in this field disables I2C access to the remote Deserializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 0 |
RW |
Freeze Device ID
Port0/Port1 |
Freeze Deserializer Device ID.
1: Prevents auto-loading of the Deserializer Device ID by the Bidirectional Control Channel. The ID will be frozen at the value written.
0: Allows auto-loading of the Deserializer Device ID from the Bidirectional Control Channel.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 7 |
0x07 |
Slave ID[0] |
7:1 |
RW |
0x00 |
Slave ID 0
Port0/Port1 |
7-bit I2C address of the remote Slave 0 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 0.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 0 |
|
|
Reserved. |
| 8 |
0x08 |
Slave Alias[0] |
7:1 |
RW |
0x00 |
Slave Alias ID 0
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 0 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 0 register. A value of 0 in this field disables access to the remote Slave 0.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 0 |
|
|
Reserved. |
| 10 |
0x0A |
CRC Errors |
7:0 |
R |
0x00 |
CRC Error LSB
Port0/Port1 |
Number of back channel CRC errors – 8 least significant bits. Cleared by 0x04[5].
If PORT1_SEL is set, this field refers to Port1 operation. |
| 11 |
0x0B |
7:0 |
R |
0x00 |
CRC Error MSB
Port0/Port1 |
Number of back channel CRC errors – 8 most significant bits. Cleared by 0x04[5].
If PORT1_SEL is set, this field refers to Port1 operation. |
| 12 |
0x0C |
General Status |
7:4 |
|
0x00 |
|
Reserved. |
| 3 |
R |
BIST CRC Error
Port0/Port1 |
Back channel CRC error(s) during BIST communication with Deserializer. This bit is cleared upon loss of link, restart of BIST, or assertion of CRC Error Reset bit in 0x04[5].
0: No CRC errors detected during BIST.
1: CRC error(s) detected during BIST.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 2 |
R |
PCLK Detect |
Pixel clock status:
0: Valid PCLK not detected at OpenLDI input.
1: Valid PCLK detected at OpenLDI input.
When the OpenLDI input is suddenly removed, this bit will remain asserted until and invalid (out of range) clock is applied. |
| 1 |
R |
DES Error
Port0/Port1 |
CRC error(s) during normal communication with Deserializer. This bit is cleared upon loss of link or assertion of 0x04[5].
0: No CRC errors detected.
1: CRC error(s) detected.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 0 |
R |
LINK Detect
Port0/Port1 |
LINK detect status:
0: Cable link not detected.
1: Cable link detected.
If PORT1_SEL is set, this field refers to Port1 operation. |
| 13 |
0x0D |
GPIO0 Configuration
(If PORT1_SEL is set, this register controls the D_GPIO0 pin) |
7:4 |
R |
0x00 |
Revision ID |
Revision ID:
0010: Production device. |
| 3 |
RW |
GPIO0 Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH. |
| 2:0 |
RW |
GPIO0 Mode |
Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE.
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. |
| 14 |
0x0E |
GPIO1 and GPIO2 Configuration
(If PORT1_SEL is set, this register controls the D_GPIO1 and D_GPIO2 pins) |
7 |
RW |
0x00 |
GPIO2 Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH. |
| 6:4 |
RW |
GPIO2 Mode |
Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE.
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. |
| 3 |
RW |
GPIO1 Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH. |
| 2:0 |
RW |
GPIO1 Mode |
Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE.
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. |
| 15 |
0x0F |
GPIO3 Configuration
(If PORT1_SEL is set, this register controls the D_GPIO3 pin) |
7:4 |
|
0x00 |
|
Reserved. |
| 3 |
RW |
GPIO3 Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled.
0: Output LOW (default).
1: Output HIGH. |
| 2:0 |
RW |
GPIO3 Mode |
Determines operating mode for the GPIO pin:
x00: Functional input mode.
x10: TRI-STATE.
001: GPIO mode, output.
011: GPIO mode, input.
101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss.
111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. |
| 16 |
0x10 |
GPIO5_REG and GPIO6_REG Configuration |
7 |
RW |
0x00 |
GPIO6_REG Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH. |
| 6 |
|
|
Reserved. |
| 5:4 |
RW |
GPIO6_REG Mode |
Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE.
01: GPIO mode, output.
11: GPIO mode; input. |
| 3 |
RW |
GPIO5_REG Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH. |
| 2 |
|
|
Reserved. |
| 1:0 |
RW |
GPIO5_REG Mode |
Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE.
01: GPIO mode, output.
11: GPIO mode; input. |
| 17 |
0x11 |
GPIO7_REG and GPIO8_REG Configuration |
7 |
RW |
0x00 |
GPIO8_REG Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH. |
| 6 |
|
|
Reserved. |
| 5:4 |
RW |
GPIO8_REG Mode |
Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE.
01: GPIO mode, output.
11: GPIO mode; input. |
| 3 |
RW |
GPIO7_REG Output Value |
Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output.
0: Output LOW (default).
1: Output HIGH. |
| 2 |
|
|
Reserved. |
| 1:0 |
RW |
GPIO7_REG Mode |
Determines operating mode for the GPIO pin:
00: Functional input mode.
10: TRI-STATE.
01: GPIO mode, output.
11: GPIO mode; input. |
| 18 |
0x12 |
Data Path Control |
7 |
|
0x00 |
|
Reserved. |
| 6 |
RW |
PASS RGB |
Setting this bit causes RGB data to be sent independent of DE in UH devices, which can be used to allow UH devices to interoperate with UB devices. However, setting this bit prevents HDCP operation and blocks packetized audio. This bit does not need to be set in UB devices.
1: Pass RGB independent of DE.
0: Normal operation. |
| 5 |
RW |
DE Polarity |
This bit indicates the polarity of the DE (Data Enable) signal.
1: DE is inverted (active low, idle high).
0: DE is positive (active high, idle low). |
| 4 |
RW |
I2S Repeater Regen |
Regenerate I2S data from Repeater I2S pins.
0: Repeater pass through I2S from video pins (default).
1: Repeater regenerate I2S from I2S pins. |
| 3 |
RW |
I2S CHANNEL B ENABLE OVERRIDE |
1: Set I2S Channel B Enable from reg_12[0].
0: I2S Channel B Disabled. |
| 2 |
RW |
Video Select |
Selects 18-bit or 24-bit video.
1: Select 18-bit video mode.
0: Select 24-bit video mode. |
| 1 |
RW |
I2S Transport Select |
Select I2S transport mode:
0: Enable I2S Data Island transport (default).
1: Enable I2S Data Forward Channel Frame transport. |
| 0 |
RW |
I2S CHANNEL B ENABLE |
I2S Channel B Enable.
1: Enable I2S Channel B on B1 input.
0: I2S Channel B disabled.
Note that in a repeater, this bit may be overridden by the in-band I2S mode detection. |
| 19 |
0x13 |
General-Purpose Control |
7 |
R |
0x88 |
MODE_SEL1 Done |
Indicates MODE_SEL1 value has stabilized and has been latched. |
| 6:4 |
R |
MODE_SEL1 Decode |
Returns the 3-bit decode of the MODE_SEL1 pin. |
| 3 |
R |
MODE_SEL0 Done |
Indicates MODE_SEL0 value has stabilized and has been latched. |
| 2:0 |
R |
MODE_SEL0 Decode |
Returns the 3-bit decode of the MODE_SEL0 pin. |
| 20 |
0x14 |
BIST Control |
7:3 |
|
0x00 |
|
Reserved. |
| 2:1 |
RW |
OSC Clock Source |
Allows choosing different OSC clock frequencies for forward channel frame.
OSC Clock Frequency in Functional Mode when PCLK is not present and 0x03[2]=1.
00: 50MHz Oscillator.
01: 50 MHz Oscillator.
10: 100 MHz Oscillator.
11: 25 MHz Oscillator.
Clock Source in BIST mode i.e. when 0x14[0]=1.
00: External Pixel Clock.
01: 50 MHz Oscillator.
10: 100 MHz Oscillator.
11: 25 MHz Oscillator. |
| 0 |
R |
BIST Enable |
BIST control:
0: Disabled (default).
1: Enabled. |
| 21 |
0x15 |
I2C Voltage Select |
7:0 |
RW |
0x01 |
I2C Voltage Select |
Selects 1.8 or 3.3V for the I2C_SDA and I2C_SCL pins. This register is loaded from the I2C_VSEL strap option from the I2CSEL pin at power-up. At power-up, a logic LOW will select 3.3V operation, while a logic HIGH (pull-up resistor attached) will select 1.8V signaling. Issuing either of the digital resets via register 0x01 will cause the I2C_VSEL value to be reset to 3.3V operation.
Reads of this register return the status of the I2C_VSEL control:
0: Select 1.8V signaling.
1: Select 3.3V signaling.
This bit may be overwritten via register access or via eFuse program by writing an 8-bit value to this register:
Write 0xb5 to set I2C_VSEL.
Write 0xb6 to clear I2C_VSEL. |
| 22 |
0x16 |
BCC Watchdog Control |
7:1 |
RW |
0xFE |
Timer Value |
The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0. |
| 0 |
RW |
Timer Control |
Disable Bidirectional Control Channel (BCC) Watchdog Timer:
0: Enable BCC Watchdog Timer operation (default).
1: Disable BCC Watchdog Timer operation. |
| 23 |
0x17 |
I2C Control |
7 |
RW |
0x1E |
I2C Pass All |
0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs matching either the remote Deserializer Slave ID or the remote Slave ID (default).
1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs that do not match the Serializer I2C Slave ID. |
| 6:4 |
RW |
SDA Hold Time |
Internal SDA hold time:
Configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 40 nanoseconds. |
| 3:0 |
RW |
I2C Filter Depth |
Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 nanoseconds. |
| 24 |
0x18 |
SCL High Time |
7:0 |
RW |
0xA1 |
SCL HIGH Time |
I2C Master SCL High Time:
This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the internal oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional oscillator clock periods.
Min_delay = 38.0952ns * (TX_SCL_HIGH + 5). |
| 25 |
0x19 |
SCL Low Time |
7:0 |
RW |
0xA5 |
SCL LOW Time |
I2C SCL Low Time:
This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the internal oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional clock periods.
Min_delay = 38.0952ns * (TX_SCL_LOW + 5). |
| 26 |
0x1A |
Data Path Control 2 |
7 |
RW |
0x00 |
BLOCK_REPEATER_I2S_MODE |
Block automatic I2S mode configuration in repeater.
0: I2S mode (2-channel, 4-channel, or surround) is detected from the in-band audio signaling in a repeater.
1: Disable automatic detection of I2S mode. |
| 6:2 |
|
|
|
Reserved. |
| 1 |
RW |
0x00 |
MODE_28B |
Enable 28-bit Serializer Mode.
0: 24-bit high-speed data + 3 low-speed control (DE, HS, VS).
1: 28-bit high-speed data mode. |
| 0 |
RW |
I2S Surround |
Enable 5.1- or 7.1-channel I2S audio transport:
0: 2-channel or 4-channel I2S audio is enabled as configured in register 0x12 bits 3 and 0 (default).
1: 5.1- or 7.1-channel audio is enabled.
Note that I2S Data Island Transport is the only option for surround audio. Also note that in a repeater, this bit may be overridden by the in-band I2S mode detection. |
| 27 |
0x1B |
BIST BC Error Count |
7:0 |
R |
0x00 |
BIST BC Error
Port0/Port1 |
BIST back channel CRC error counter.
This register stores the back channel CRC error count during BIST Mode (saturates at 255 errors). Clears when a new BIST is initiated or by 0x04[5].
If PORT1_SEL is set, this register indicates Port1 operation. |
| 28 |
0x1C |
GPIO Pin Status 1 |
7 |
R |
0x00 |
GPIO7_REG Pin Status |
GPIO7_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode. |
| 6 |
R |
GPIO6_REG Pin Status |
GPIO6_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode. |
| 5 |
R |
GPIO5_REG Pin Status |
GPIO5_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode. |
| 4 |
|
|
Reserved. |
| 3 |
R |
GPIO3 Pin Status
D_GPIO3 Pin Status |
GPIO3 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO3 operation. |
| 2 |
R |
GPIO2 Pin Status
D_GPIO2 Pin Status |
GPIO2 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO2 operation. |
| 1 |
R |
GPIO1 Pin Status
D_GPIO1 Pin Status |
GPIO1 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO1 operation. |
| 0 |
R |
GPIO0 Pin Status
D_GPIO0 Pin Status |
GPIO0 input pin status.
Note: status valid only if pin is set to GPI (input) mode.
If PORT1_SEL is set, this register indicates D_GPIO0 operation. |
| 29 |
0x1D |
GPIO Pin Status 2 |
7:1 |
|
0x00 |
|
Reserved |
| 0 |
R |
GPIO8_REG Pin Status |
GPIO8_REG input pin status.
Note: status valid only if pin is set to GPI (input) mode. |
| 30 |
0x1E |
Port Select |
7:3 |
|
0x01 |
|
Reserved. |
| 2 |
RW |
PORT1_I2C_EN |
Port1 I2C Enable: Enables secondary I2C address. The second I2C address provides access to port1 registers as well as registers that are shared between ports 0 and 1. The second I2C address value will be set to DeviceID + 1 (7-bit format). The PORT1_I2C_EN bit must also be set to allow accessing remote devices over the second link when the device is in Replicate mode. |
| 1 |
RW |
PORT1_SEL |
Selects Port 1 for Register Access from primary I2C Address. For writes, Port 1 registers and shared registers will both be written. For reads, Port 1 registers and shared registers will be read. This bit must be cleared to read Port 0 registers.
If this bit is set, GPIO[3:0] registers control operation for D_GPIO[3:0] registers.
This bit is ignored if PORT1_I2C_EN is set. |
| 0 |
RW |
PORT0_SEL |
Selects Port 0 for Register Access from primary I2C Address. For writes, Port 0 registers and shared registers will both be written. For reads, Port 0 registers and shared registers will be read. Note that if PORT1_SEL is also set, then Port 1 registers will be read.
This bit is ignored if PORT1_I2C_EN is set. |
| 31 |
0x1F |
Frequency Counter |
7:0 |
RW |
0x00 |
Frequency Count |
Frequency Counter control: A write to this register will enable a frequency counter to count the number of pixel clock during a specified time interval. The time interval is equal to the value written multiplied by the oscillator clock period (nominally 40ns). A read of the register returns the number of pixel clock edges seen during the enabled interval. The frequency counter will freeze at 0xff if it reaches the maximum value. The frequency counter will provide a rough estimate of the pixel clock period. If the pixel clock frequency is known, the frequency counter may be used to determine the actual oscillator clock frequency. |
| 32 |
0x20 |
Deserializer Capabilities |
7 |
RW |
0x00 |
FREEZE DES CAP
Port0/Port1 |
Freeze Deserializer Capabilities. Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel. The Capabilities will be frozen at the values written in registers 0x20 and 0x21. |
| 6 |
|
|
|
Reserved. |
| 5 |
RW |
|
Send_Freq
Port0/Port1 |
Send Frequency Training Pattern. |
| 4 |
RW |
0x00 |
Send_EQ
Port0/Port1 |
Send Equalization Training Pattern. |
| 3 |
RW |
Dual Link Capable
Port0/Port1 |
Dual link capabilities. Indicates if the Deserializer is capable of dual link operation. |
| 2 |
RW |
Dual Channel
Port0/Port1 |
In a dual-link device, indicates if this is the primary or secondary channel.
0: Primary channel (channel 0).
1: Secondary channel (channel 1). |
| 1 |
RW |
VID_24B_HD_AUD
Port0/Port1 |
Deserializer supports 24-bit video concurrently with HD audio. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. |
| 0 |
RW |
DES_CAP_FC_GPIO
Port0/Port1 |
Deserializer supports GPIO in the Forward Channel Frame. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. |
| 38 |
0x26 |
Link Detect Control |
7:2 |
|
|
|
Reserved. |
| 1:0 |
RW |
0x00 |
LINK DETECT TIMER |
Bidirectional Control Channel Link Detect Timer. This field configures the link detection timeout period. If the timer expires without valid communication over the reverse channel, link detect will be deasserted.
00: 325 microseconds.
01: 162 microseconds.
10: 650 microseconds.
11: 1.3 milliseconds. |
| 64 |
0x40 |
ANA_IA_CNTL |
7:5 |
|
0x00 |
|
Reserved. |
| 4:2 |
RW |
ANA_IA_SEL |
Analog register select
Selects target for register access
000b: Disabled
001b - 011b: Reserved
100b: OLDI Registers
101b: FPD3 TX Registers
11xb: Reserved |
| 1 |
RW |
ANA_AUTO_INC |
Analog Register Auto Increment
0: Disable auto-increment mode
1: Enable auto-increment mode. Upon completion of a read or write, the register address will automatically be incremented by 1. |
| 0 |
RW |
ANA_IA_READ |
Start Analog Register Read
0: Write analog register
1: Read analog register |
| 65 |
0x41 |
ANA_IA_ADDR |
7:0 |
RW |
0x00 |
ANA_IA_ADDR |
Analog register offset
This register contains the 8-bit register offset for the indirect access. |
| 66 |
0x42 |
ANA_IA_DATA |
7:0 |
RW |
0x00 |
ANA_IA_DATA |
Analog register data
Writing this register will cause an indirect write of the ANA_IA_DATA value to the selected analog block register. Reading this register will return the value of the selected analog block register. |
| 72 |
0x48 |
APB_CTL |
7:5 |
|
|
|
Reserved. |
| 4:3 |
RW |
0x00 |
APB_SELECT |
APB Select: Selects target for register access:
00 : Reserved.
01 : Reserved.
10 : Configuration Data (read only).
11 : Die ID (read only). |
| 2 |
RW |
APB_AUTO_INC |
APB Auto Increment:
Enables auto-increment mode. Upon completion of an APB read or write, the APB address will automatically be incremented by 0x1. |
| 1 |
RW |
APB_READ |
Start APB Read:
Setting this bit to a 1 will begin an APB read. Read data will be available in the APB_DATA0 register. The APB_ADR0 register should be programmed prior to setting this bit. This bit will be cleared when the read is complete. |
| 0 |
RW |
APB_ENABLE |
APB Interface Enable:
Set to a 1 to enable the APB interface. The APB_SELECT bits indicate what device is selected. |
| 73 |
0x49 |
APB_ADR0 |
7:0 |
RW |
0x00 |
APB_ADR0 |
APB address byte 0 (LSB). |
| 75 |
0x4B |
APB_DATA0 |
7:0 |
RW |
0x00 |
APB_DATA0 |
Byte 0 (LSB) of the APB Interface Data. |
| 79 |
0x4F |
BRIDGE_CTL |
7 |
RW |
Strap |
OLDI_MAPSEL |
OpenLDI Bit Map Select.
Determines data mapping on the OpenLDI interface.
0: SPWG mapping.
1: OpenLDI mapping.
OLDI_MAPSEL is initially loaded from the MODE_SEL1 pin strap options. |
| 6 |
RW |
Strap |
OLDI_IN_MODE |
OpenLDI Receiver Input Mode.
Determines operating mode of OpenLDI Receive Interface.
0: Dual-pixel mode.
1: Single-pixel mode.
OLDI_IN_MODE is initially loaded from the MODE_SEL0 pin strap options. |
| 5 |
RW |
0x00 |
OLDI_IN_SWAP |
OLDI Receive input swap:
Swaps OLDI input ports. If OLDI_IN_MODE is set to 1 (single), then the secondary port is used. If OLDI_IN_MODE is set to 0 (dual), then the ports are swapped. |
| 4:2 |
|
|
|
Reserved. |
| 1 |
RW |
0x00 |
CFG_INIT |
Initialize Configuration from Non-Volatile Memory:
Causes a reload of the configuration data from the non-volatile memory. This bit will be cleared when the initialization is complete. |
| 0 |
|
|
|
Reserved. |
| 80 |
0x50 |
BRIDGE_STS |
7:6 |
|
|
|
Reserved. |
| 5 |
R |
0x00 |
HDCP_INT |
HDCP Interrupt Status: Indicates an HDCP Transmitter Interrupt is pending. HDCP Transmit interrupts are serviced through the HDCP Interrupt Control and Status registers. |
| 4 |
R |
INIT_DONE |
Initialization Done: Initialization sequence has completed. This step will complete after configuration complete (CFG_DONE). |
| 3 |
|
|
|
Reserved. |
| 2 |
R |
0x00 |
CFG_DONE |
Configuration Complete: Indicates automatic configuration has completed. This step will complete prior to initialization complete (INIT_DONE). |
| 1 |
R |
0x01 |
CFG_CKSUM |
Configuration checksum status: Indicates result of Configuration checksum during initialization. The device verifies the 2’s complement checksum in the last 128 bytes of the EEPROM. A value of 1 indicates the checksum passed. |
| 0 |
|
|
|
Reserved. |
| 84 |
0x54 |
BRIDGE_CFG |
7:3 |
|
|
|
Reserved. |
| 2 |
RW |
0x00 |
AUDIO_TDM |
Enable TDM Audio: Setting this bit to a 1 will enable TDM audio for the I2S audio. Parallel I2S data on the I2S pins will be serialized onto a single I2S_DA signal for sending over the serial link. |
| 1 |
RW |
0x01 |
AUDIO_MODE |
Audio Mode: Selects source for audio to be sent over the FPD-Link III downstream link.
0 :Disabled.
1 : I2S audio from I2S pins. |
| 0 |
|
|
|
Reserved. |
| 84 |
0x55 |
AUDIO_CFG |
7 |
RW |
0x00 |
TDM_2_PARALLEL |
EnableTDM to parallel I2S audio conversion: When this bit is set, the TDM to parallel I2S conversion is enabled. TDM audio data on the I2S_DA pin will be split onto four I2S data signals. |
| 6:0 |
|
|
|
Reserved. |
| 87 |
0x57 |
TDM_CONFIG |
7:4 |
|
|
|
Reserved. |
| 3 |
RW |
0x00 |
TDM_FS_MODE |
TDM Frame Sync Mode: Sets active level for the Frame Sync for the TDM audio. The Frame Sync signal provides an active pulse to indicate the first sample data on the TDM data signal.
0 : Active high Frame Sync.
1 : Active low Frame Sync (similar to I2S word select).
This bit is used for both the output of the I2S to TDM conversion and the input of the TDM to I2S conversion. |
| 2 |
RW |
0x00 |
TDM_DELAY |
TDM Data Delay: Controls data delay for TDM audio samples from the active Frame Sync edge.
0 : Data is not delayed from Frame Sync (data is left justified).
1 : Data is delayed 1 bit from Frame Sync.
This bit is used for both the output of the I2S to TDM conversion and the input of the TDM to I2S conversion. |
| 1:0 |
RW |
0x02 |
TDM_FS_WIDTH |
TDM Frame Sync Width: Indicates width of TDM Frame Sync pulse for I2S to TDM conversion.
00 : FS is 50/50 duty cycle.
01 : FS is one slot/channel wide.
1x : FS is 1 clock pulse wide. |
| 90 |
0x5A |
DUAL_STS |
7 |
R |
0x00 |
FPD3_LINK_RDY |
FPD-Link III Ready: This bit indicates that the FPD-Link III has detected a valid downstream connection and determined capabilities for the downstream link. |
| 6 |
R |
FPD3_TX_STS |
FPD-Link III transmit status:
This bit indicates that the FPD-Link III transmitter is active and the receiver is LOCKED to the transmit clock. It is only asserted once a valid input has been detected, and the FPD-Link III transmit connection has entered the correct mode (Single vs. Dual mode). |
| 5:4 |
R |
FPD3_PORT_STS |
FPD-Link III Port Status: If FPD3_TX_STS is set to a 1, this field indicates the port mode status as follows:
00: Dual FPD-Link III Transmitter mode.
01: Single FPD-Link III Transmit on port 0.
10: Single FPD-Link III Transmit on port 1.
11: Replicate FPD-Link III Transmit on both ports. |
| 3 |
R |
OLDI_CLK_DET |
OpenLDI clock detect indication from the OpenLDI PLL controller. |
| 2 |
R |
OLDI_PLL_LOCK |
OpenLDI PLL lock status:
Indicates the OpenLDI PLL has locked to the incoming OpenLDI clock. |
| 1 |
R |
NO_OLDI_CLK |
No OpenLDI clock detected:
This bit indicates the Frequency Detect Circuit did not detect an OpenLDI clock greater than the value specified in the FREQ_LOW register. |
| 0 |
R |
FREQ_STABLE |
OLDI Frequency is stable:
Indicates the Frequency Detection circuit has detected a stable OLDI clock frequency. |
| 91 |
0x5B |
DUAL_CTL1 |
7 |
RW |
Strap |
FPD3_COAX_MODE |
FPD-Link III Coax Mode: Enables configuration for the FPD-Link III Interface cabling type:
0 : Twisted Pair.
1 : Coax.
This bit is loaded from the MODE_SEL1 pin at power-up. |
| 6 |
RW |
0x20 |
DUAL_SWAP |
Dual Swap Control:
Indicates current status of the Dual Swap control. If automatic correction of Dual Swap is disabled via the DISABLE_DUAL_SWAP control, this bit may be modified by software. |
| 5 |
RW |
RST_PLL_FREQ |
Reset FPD-Link III PLL on Frequency Change: When set to a 1, frequency changes detected by the Frequency Detect circuit will result in a reset of the FPD3 PLL. |
| 4 |
RW |
FREQ_DET_PLL |
Frequency Detect Select PLL Clock. Determines the clock source for the Frequency detection circuit:
0 : OpenLDI clock (prior to PLL).
1: OpenLDI PLL clock. |
| 3 |
RW |
DUAL_ALIGN_DE |
Dual Align on DE: In dual-link mode, if this bit is set to a 1, the odd/even data will be sent on the primary/secondary links respectively, based on the assertion of DE. If this bit is set to a 0, data will be sent on alternating links without regard to odd/even pixel position. |
| 2 |
RW |
DISABLE_DUAL |
Disable Dual Mode: During Auto-detect operation, setting this bit to a 1 will disable Dual FPD-Link III operation.
0: Normal Auto-detect operation.
1: Only Single or Replicate operation supported.
This bit will have no effect if FORCE_LINK is set. |
| 1 |
RW |
FORCE_DUAL |
Force dual mode:
When FORCE_LINK bit is set, the value on this bit controls single versus dual operation:
0: Single FPD-Link III Transmitter mode.
1: Dual FPD-Link III Transmitter mode. |
| 0 |
RW |
FORCE_LINK |
Force Link Mode: Forces link to dual or single mode, based on the FORCE_DUAL control setting. If this bit is 0, mode setting will be automatically set based on downstream device capabilities as well as the incoming data frequency.
1 : Forced Single or Dual FPD-Link III mode.
0 : Auto-Detect FPD-Link III mode. |
| 92 |
0x5C |
DUAL_CTL2 |
7 |
RW |
0x00 |
DISABLE_DUAL_SWAP |
Disable Dual Swap: Prevents automatic correction of swapped Dual link connection. Setting this bit allows writes to the DUAL_SWAP control in the DUAL_CTL1 register. |
| 6 |
RW |
FORCE_LINK_RDY |
Force Link Ready.
Forces link ready indication, bypassing back channel link detection. |
| 5 |
RW |
FORCE_CLK_DET |
Force Clock Detect.
Forces the OpenLDI clock detect circuit to indicate presence of a valid input clock. This bypasses the clock detect circuit, allowing operation with an input clock that does not meet frequency or stability requirements. |
| 4:3 |
RW |
FREQ_STBL_THR |
Frequency Stability Threshold: The Frequency detect circuit can be used to detect a stable clock frequency. The Stability Threshold determines the amount of time required for the clock frequency to stay within the FREQ_HYST range to be considered stable:
00 : 160us.
01 : 640us.
10 : 1.28ms.
11 : 2.55ms. |
| 2:0 |
RW |
0x02 |
FREQ_HYST |
Frequency Detect Hysteresis: The Frequency detect hysteresis setting allows ignoring minor fluctuations in frequency. A new frequency measurement will be captured only if the measured frequency differs from the current measured frequency by more than the FREQ_HYST setting. The FREQ_HYST setting is in MHz. |
| 93 |
0x5D |
FREQ_LOW |
7 |
|
|
|
Reserved. |
| 6 |
RW |
0x00 |
OLDI_RST_MODE |
OLDI Phy Reset Mode:
0 : Reset OLDI Phy on change in mode or frequency.
1 : Don't reset OLDI Phy on change in mode or frequency. |
| 5:0 |
RW |
0x06 |
FREQ_LO_THR |
Frequency Low Threshold: Sets the low threshold for the OLDI Clock frequency detect circuit in MHz. This value is used to determine if the OLDI clock frequency is too low for proper operation. |
| 94 |
0x5E |
FREQ_HIGH |
7 |
|
|
|
Reserved. |
| 6:0 |
RW |
44 |
FREQ_HI_THR |
Frequency High Threshold: Sets the high threshold for the OLDI Clock frequency detect circuit in MHz. |
| 95 |
0x5F |
OpenLDI Frequency |
7:0 |
R |
0x00 |
OLDI_FREQ |
OLDI Pixel Frequency:
Returns the value of the OLDI pixel Frequency of the video data. This register indicates the pixel rate for the incoming data. If the OLDI interface is in single-pixel mode, the pixel frequency is the same as the OLDI frequency. If the OLDI interface is in dual-pixel mode, the pixel frequency is 2x the OLDI frequency. A value of 0 indicates the OLDI receiver is not detecting a valid signal.
When the OpenLDI input is suddenly removed, this register will retain its value. |
| 96 |
0x60 |
SPI_TIMING1 |
7:4 |
RW |
0x02 |
SPI_HOLD |
SPI Data Hold from SPI clock: These bits set the minimum hold time for SPI data following the SPI clock sampling edge. In addition, this also sets the minimum active pulse width for the SPI output clock.
Hold = (SPI_HOLD + 1) * 40ns.
For example, default setting of 2 will result in 120ns data hold time. |
| 3:0 |
RW |
0x02 |
SPI_SETUP |
SPI Data Setup to SPI Clock: These bits set the minimum setup time for SPI data to the SPI clock active edge. In addition, this also sets the minimum inactive width for the SPI output clock.
Setup = (SPI_SETUP + 1) * 40ns.
For example, default setting of 2 will result in 120ns data setup time. |
| 97 |
0x61 |
SPI_TIMING2 |
7:4 |
|
|
|
Reserved. |
| 3:0 |
RW |
0x00 |
SPI_SS_SETUP |
SPI Slave Select Setup: This field controls the delay from assertion of the Slave Select low to initial data timing. Delays are in units of 40ns.
Delay = (SPI_SS_SETUP + 1) * 40ns. |
| 98 |
0x62 |
SPI_CONFIG |
7 |
R |
0x00 |
SPI_MSTR_OVER |
SPI Master Overflow Detection: This flag is set if the SPI Master detects an overflow condition. This occurs if the SPI Master is unable to regenerate the remote SPI data at a fast enough rate to keep up with data arriving from the remote Deserializer. If this condition occurs, it suggests the SPI_SETUP and SPI_HOLD times should be set to smaller values. This flag is cleared by setting the SPI_CLR_OVER bit in this register. |
| 6:3 |
|
|
|
Reserved. |
| 2 |
RW |
0x00 |
SPI_CLR_OVER |
Clear SPI Master Overflow Flag: Setting this bit to 1 will clear the SPI Master Overflow Detection flag (SPI_MSTR_OVER). This bit is not self-clearing and must be set back to 0. |
| 1 |
R |
0x00 |
SPI_CPHA |
SPI Clock Phase setting: Determines which phase of the SPI clock is used for sampling data.
0: Data sampled on leading (first) clock edge.
1: Data sampled on trailing (second) clock edge.
This bit is read-only, with a value of 0. The DS90UH947-Q1 does not support CPHA of 1. |
| 0 |
RW |
0x00 |
SPI_CPOL |
SPI Clock Polarity setting: Determines the base (inactive) value of the SPI clock.
0: base value of the clock is 0.
1: base value of the clock is 1.
This bit affects both capture and propagation of SPI signals. |
| 100 |
0x64 |
Pattern Generator Control |
7:4 |
RW |
0x10 |
Pattern Generator Select |
Fixed Pattern Select
Selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled.
xxxx: normal/inverted.
0000: Checkerboard.
0001: White/Black (default).
0010: Black/White.
0011: Red/Cyan.
0100: Green/Magenta.
0101: Blue/Yellow.
0110: Horizontal Black-White/White-Black.
0111: Horizontal Black-Red/White-Cyan.
1000: Horizontal Black-Green/White-Magenta.
1001: Horizontal Black-Blue/White-Yellow.
1010: Vertical Black-White/White-Black.
1011: Vertical Black-Red/White-Cyan.
1100: Vertical Black-Green/White-Magenta.
1101: Vertical Black-Blue/White-Yellow.
1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers.
1111: VCOM.
See TI App Note AN-2198. |
| 3 |
|
|
Reserved. |
| 2 |
RW |
Color Bars Pattern |
Enable color bars:
0: Color Bars disabled (default).
1: Color Bars enabled.
Overrides the selection from reg_0x64[7:4]. |
| 1 |
RW |
VCOM Pattern Reverse |
Reverse order of color bands in VCOM pattern:
0: Color sequence from top left is (YCBR) (default).
1: Color sequence from top left is (RBCY). |
| 0 |
RW |
Pattern Generator Enable |
Pattern Generator enable:
0: Disable Pattern Generator (default).
1: Enable Pattern Generator. |
| 101 |
0x65 |
Pattern Generator Configuration |
7 |
|
0x00 |
|
Reserved. |
| 6 |
RW |
Checkerboard Scale |
Scale Checkered Patterns:
0: Normal operation (each square is 1x1 pixel) (default).
1: Scale checkered patterns (VCOM and checkerboard) by 8 (each square is 8x8 pixels).
Setting this bit gives better visibility of the checkered patterns. |
| 5 |
RW |
Custom Checkerboard |
Use Custom Checkerboard Color:
0: Use white and black in the Checkerboard pattern (default).
1: Use the Custom Color and black in the Checkerboard pattern. |
| 4 |
RW |
PG 18–bit Mode |
18-bit Mode Select:
0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness (default).
1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits. |
| 3 |
RW |
External Clock |
Select External Clock Source:
0: Selects the internal divided clock when using internal timing (default).
1: Selects the external pixel clock when using internal timing.
This bit has no effect in external timing mode (PATGEN_TSEL = 0). |
| 2 |
RW |
Timing Select |
Timing Select Control:
0: The Pattern Generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals (default).
1: The Pattern Generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers.
See TI App Note AN-2198. |
| 1 |
RW |
Color Invert |
Enable Inverted Color Patterns:
0: Do not invert the color output (default).
1: Invert the color output.
See TI App Note AN-2198. |
| 0 |
RW |
Auto Scroll |
Auto Scroll Enable:
0: The Pattern Generator retains the current pattern (default).
1: The Pattern Generator will automatically move to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time (PGFT) register.
See TI App Note AN-2198. |
| 102 |
0x66 |
PGIA |
7:0 |
RW |
0x00 |
PG Indirect Address |
This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data register.
See TI App Note AN-2198 |
| 103 |
0x67 |
PGID |
7:0 |
RW |
0x00 |
PG Indirect Data |
When writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the read back value.
See TI App Note AN-2198 |
| 112 |
0x70 |
Slave ID[1] |
7:1 |
RW |
0x00 |
Slave ID 1
Port0/Port1 |
7-bit I2C address of the remote Slave 1 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 1.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 113 |
0x71 |
Slave ID[2] |
7:1 |
RW |
0x00 |
Slave ID 2
Port0/Port1 |
7-bit I2C address of the remote Slave 2 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 2.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 114 |
0x72 |
Slave ID[3] |
7:1 |
RW |
0x00 |
Slave ID 3
Port0/Port1 |
7-bit I2C address of the remote Slave 3 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 3.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 115 |
0x73 |
Slave ID[4] |
7:1 |
RW |
0x00 |
Slave ID 4
Port0/Port1 |
7-bit I2C address of the remote Slave 4 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 4.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 116 |
0x74 |
Slave ID[5] |
7:1 |
RW |
0x00 |
Slave ID 5
Port0/Port1 |
7-bit I2C address of the remote Slave 5 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 5, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 5.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 117 |
0x75 |
Slave ID[6] |
7:1 |
RW |
0x00 |
Slave ID 6
Port0/Port1 |
7-bit I2C address of the remote Slave 6 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 6.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 118 |
0x76 |
Slave ID[7] |
7:1 |
RW |
0x00 |
Slave ID 7
Port0/Port1 |
7-bit I2C address of the remote Slave 7 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 7.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 119 |
0x77 |
Slave Alias[1] |
7:1 |
RW |
0x00 |
Slave Alias ID 1
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 1 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 1 register. A value of 0 in this field disables access to the remote Slave 1.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 120 |
0x78 |
Slave Alias[2] |
7:1 |
RW |
0x00 |
Slave Alias ID 2
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 2 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 2 register. A value of 0 in this field disables access to the remote Slave 2.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 121 |
0x79 |
Slave Alias[3] |
7:1 |
RW |
0x00 |
Slave Alias ID 3
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 3 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 3 register. A value of 0 in this field disables access to the remote Slave 3.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 122 |
0x7A |
Slave Alias[4] |
7:1 |
RW |
0x00 |
Slave Alias ID 4
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 4 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 4 register. A value of 0 in this field disables access to the remote Slave 4.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 123 |
0x7B |
Slave Alias[5] |
7:1 |
RW |
0x00 |
Slave Alias ID 5
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 5 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 5 register. A value of 0 in this field disables access to the remote Slave 5.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 124 |
0x7C |
Slave Alias[6] |
7:1 |
RW |
0x00 |
Slave Alias ID 6
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 6 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 6 register. A value of 0 in this field disables access to the remote Slave 6.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 125 |
0x7D |
Slave Alias[7] |
7:1 |
RW |
0x00 |
Slave Alias ID 7
Port0/Port1 |
7-bit Slave Alias ID of the remote Slave 7 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 7 register. A value of 0 in this field disables access to the remote Slave 7.
If Port1_SEL is set, this register controls Port1 operation. |
| 0 |
|
|
Reserved. |
| 128 |
0x80 |
RX_BKSV0 |
7:0 |
R |
0x00 |
BKSV0 |
BKSV0: Value of byte0 of the Receiver KSV. |
| 129 |
0x81 |
RX_BKSV1 |
7:0 |
R |
0x00 |
BKSV1 |
BKSV1: Value of byte1 of the Receiver KSV. |
| 130 |
0x82 |
RX_BKSV2 |
7:0 |
R |
0x00 |
BKSV2 |
BKSV2: Value of byte2 of the Receiver KSV. |
| 131 |
0x83 |
RX_BKSV3 |
7:0 |
R |
0x00 |
BKSV3 |
BKSV3: Value of byte3 of the Receiver KSV. |
| 132 |
0x84 |
RX_BKSV4 |
7:0 |
R |
0x00 |
BKSV4 |
BKSV4: Value of byte4 of the Receiver KSV. |
| 144 |
0x90 |
TX_KSV0 |
7:0 |
R |
0x00 |
TX_KSV0 |
TX_KSV0: Value of byte0 of the Transmitter KSV. |
| 145 |
0x91 |
TX_KSV1 |
7:0 |
R |
0x00 |
TX_KSV1 |
TX_KSV1: Value of byte1 of the Transmitter KSV. |
| 146 |
0x92 |
TX_KSV2 |
7:0 |
R |
0x00 |
TX_KSV2 |
TX_KSV2: Value of byte2 of the Transmitter KSV. |
| 147 |
0x93 |
TX_KSV3 |
7:0 |
R |
0x00 |
TX_KSV3 |
TX_KSV3: Value of byte3 of the Transmitter KSV. |
| 148 |
0x94 |
TX_KSV4 |
7:0 |
R |
0x00 |
TX_KSV4 |
TX_KSV4: Value of byte4 of the Transmitter KSV. |
| 160 |
0xA0 |
RX_BCAPS |
7 |
|
|
|
Reserved. |
| 6 |
R |
0x00 |
Repeater |
Repeater: Indicates if the attached Receiver supports downstream connections. This bit is valid once the Bksv is ready as indicated by the BKSV_RDY bit in the HDCP. |
| 5 |
R |
0x00 |
KSV_FIFO_RDY |
KSV FIFO Ready: Indicates the receiver has built the list of attached KSVs and computed the verification value V’. |
| 4 |
R |
0x01 |
FAST_I2C |
Fast I2C: The HDCP Receiver supports fast I2C. Since the I2C is embedded in the serial data, this bit is not relevant. |
| 3:2 |
R |
|
|
Reserved. |
| 1 |
R |
0x01 |
FEATURES_1_1 |
1.1_Features: The HDCP Receiver supports the Enhanced Encryption Status Signaling (EESS), Advance Cipher, and Enhanced Link Verification options. |
| 0 |
R |
0x01 |
FAST_REAUTH |
Fast Reauthentication: The HDCP Receiver is capable of receiving (unencrypted) video signal during the session re-authentication. |
| 161 |
0xA1 |
RX_BSTATUS0 |
7 |
R |
0x00 |
MAX_DEVS_EXCEEDED |
Maximum Devices Exceeded: Indicates a topology error was detected. Indicates the number of downstream devices has exceeded the depth of the Repeater's KSV FIFO. |
| 6:0 |
R |
DEVICE_COUNT |
Device Count: Total number of attached downstream device. For a Repeater, this will indicate the number of downstream devices, not including the Repeater. For an HDCP Receiver that is not also a Repeater, this field will be 0. |
| 162 |
0xA2 |
RX_BSTATUS1 |
7:4 |
|
|
|
Reserved. |
| 3 |
R |
0x00 |
MAX_CASC_EXCEEDED |
Maximum Cascade Exceeded: Indicates a topology error was detected. Indicates that more than seven levels of repeaters have been cascad-ed together. |
| 2:0 |
R |
Cascade Depth |
Cascade Depth: Indicates the number of attached levels of devices for the Repeater. |
| 163 |
0xA3 |
KSV_FIFO |
7:0 |
R |
0x00 |
KSV_FIFO |
KSV FIFO: Each read of the KSV FIFO returns one byte of the KSV FIFO list composed by the downstream Receiver. |
| 192 |
0xC0 |
HDCP_DBG |
7 |
|
0x00 |
|
Reserved. |
| 6 |
RW |
HDCP_I2C_TO_DIS |
HDCP I2C Timeout Disable: Setting this bit to a 1 will disable the bus timeout function in the HDCP I2C master. When enabled, the bus timeout function allows the I2C master to assume the bus is free if no signaling occurs for more than 1 second. |
| 5 |
|
|
Reserved. |
| 4 |
RW |
DIS_RI_SYNC |
Disable Ri Synchronization check: Ri is normally checked both before and after the start of frame 128. The check at frame 127 ensures synchronization between the two. Setting this bit to a 1 will disable the check at frame 127. |
| 3 |
RW |
RGB_CHKSUM_EN |
Enable RBG video line checksum: Enables sending of ones-complement checksum for each 8-bit RBG data channel following end of each video data line. |
| 2 |
RW |
FC_TESTMODE |
Frame Counter Testmode: Speeds up frame counter used for Pj and Ri verification. When set to a 1, Pj is computed every 2 frames and Ri is computed every 16 frames. When set to a 0, Pj is computed every 16 frames and Ri is computed every 128 frames. |
| 1 |
RW |
TMR_SPEEDUP |
Timer Speedup: Speed up HDCP authentication timers. |
| 0 |
RW |
HDCP_I2C_FAST |
HDCP I2C Fast Mode Enable:
Setting this bit to a 1 will enable the HDCP I2C Master in the HDCP Receiver to operation with Fast mode timing. If set to a 0, the I2C Master will operation with Standard mode timing. This bit is mirrored in the IND_STS register. |
| 194 |
0xC2 |
HDCP_CFG |
7 |
RW |
0x80 |
ENH_LV |
Enable Enhanced Link Verification: Enables enhanced link verification. Allows checking of the encryption Pj value on every 16th frame.
1 = Enhanced Link Verification enabled.
0 = Enhanced Link Verification disabled. |
| 6 |
RW |
HDCP_EESS |
Enable Enhanced Encryption Status Signaling: Enables Enhanced Encryption Status Signaling (EESS) instead of the Original Encryption Status Signaling (OESS).
1 = EESS mode enabled.
0 = OESS mode enabled. |
| 5 |
RW |
TX_RPTR |
Transmit Repeater Enable: Enables the transmitter to act as a repeater. In this mode, the HDCP Transmitter incorporates the additional authentication steps required of an HDCP Repeater.
1 = Transmit Repeater mode enabled.
0 = Transmit Repeater mode disabled. |
| 4:3 |
RW |
ENC_MODE |
Encryption Control Mode: Determines mode for controlling whether encryption is required for video frames.
00 = Enc_Authenticated.
01 = Enc_Reg_Control.
10 = Enc_Always.
11 = Enc_InBand_Control (per frame).
If the Repeater strap option is set at power-up, Enc_InBand_Control (ENC_MODE == 11) will be se-lected. Otherwise, the default will be Enc_Authenticated mode (ENC_MODE == 00). |
| 2 |
RW |
WAIT_100MS |
Enable 100MS Wait: The HDCP 1.3 specification allows for a 100Ms wait to allow the HDCP Receiver to compute the initial encryption values. The FPD-LinkIII implementation guarantees that the Receiver will complete the computations before the HDCP Transmitter. Thus the timer is unnecessary. To enable the 100ms timer, set this bit to a 1. |
| 1 |
RW |
RX_DET_SEL |
RX Detect Select: Controls assertion of the Receiver Detect Interrupt. If set to 0, the Receiver Detect Interrupt will be asserted on detection of an FPD-Link III Receiver. If set to 1, the Receiver Detect Interrupt will also require a receive lock indication from the receiver. |
| 0 |
RW |
HDCP_AVMUTE |
Enable AVMUTE: Setting this bit to a 1 will initiate AVMUTE operation. The transmitter will ignore encryption status controls while in this state. If this bit is set to a 0, normal operation will resume. This bit may only be set if the HDCP_EESS bit is also set. |
| 195 |
0xC3 |
HDCP_CTL |
7 |
RW |
0x00 |
HDCP_RST |
HDCP Reset : Setting this bit will reset the HDCP transmitter and dis-able HDCP authentication. This bit is self-clearing. |
| 6 |
|
|
|
Reserved. |
| 5 |
RW |
0x00 |
KSV_LIST_VALID |
KSV List Valid : The controller sets this bit after validating the Repeater’s KSV List against the Key revocation list. This allows completion of the Authentication process. This bit is self-clearing. |
| 4 |
RW |
KSV_VALID |
KSV Valid : The controller sets this bit after validating the Receiver’s KSV against the Key revocation list. This allows continuation of the Authentication process. This bit will be cleared upon assertion of the KSV_RDY flag in the HDCP_STS register. Setting this bit to a 0 will have no effect. |
| 3 |
RW |
HDCP_ENC_DIS |
HDCP Encrypt Disable : Disables HDCP encryption. Setting this bit to a 1 will cause video data to be sent without encryption. Authen-tication status will be maintained. This bit is self-clearing. |
| 2 |
RW |
HDCP_ENC_EN |
HDCP Encrypt Enable : Enables HDCP encryption. When set, if the device is authenticated, encrypted data will be sent. If device is not authenticated, a blue screen will be sent. Encryption should always be enabled when video data requiring content protection is being supplied to the transmitter. When this bit is not set, video data will be sent without encryption. Note that when CFG_ENC_MODE is set to Enc_Always, this bit will be read only with a value of 1. |
| 1 |
RW |
HDCP_DIS |
HDCP Disable: Disables HDCP authentication. Setting this bit to a 1 will disable the HDCP authentication. This bit is self-clearing. |
| 0 |
RW |
HDCP_EN |
HDCP Enable/Restart: Enables HDCP authentication. If HDCP is already en-abled, setting this bit to a 1 will restart authentication. Setting this bit to a 0 will have no effect. A register read will return the current HDCP enabled status. |
| 196 |
0xC4 |
HDCP_STS |
7 |
R |
0x00 |
I2C_ERR_DET |
HDCP I2C Error Detected: This bit indicates an error was detected on the embedded communications channel with the HDCP Receiver. Setting of this bit might indicate that a problem exists on the link between the HDCP Transmitter and HDCP Receiver. This bit will be cleared on read. |
| 6 |
R |
RX_INT |
RX Interrupt : Status of the RX Interrupt signal. The signal is received from the attached HDCP Receiver and is the status on the INTB_IN pin of the HDCP Receiver. The signal is active low, so a 0 indicates an interrupt condition. |
| 5 |
R |
RX_LOCK_DET |
Receiver Lock Detect : This bit indicates that the downstream Receiver has indicated Receive Lock to incoming serial data. |
| 4 |
R |
DOWN_HPD |
Downstream Hot Plug Detect: This bit indicates a downstream repeater has reported a Hot Plug event, indicating addition of a new receiver. This bit will be cleared on read. |
| 3 |
R |
RX_DETECT |
Receiver Detect : This bit indicates that a downstream Receiver has been detected. |
| 2 |
R |
KSV_LIST_RDY |
HDCP Repeater KSV List Ready : This bit indicates that the Receiver KSV list has been read and is available in the KSV_FIFO registers. The device will wait for the controller to set the KSV_LIST_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_LIST_VALID bit. |
| 1 |
R |
KSV_RDY |
HDCP Receiver KSV Ready : This bit indicates that the Receiver KSV has been read and is available in the HDCP_BKSV registers. If the de-vice is not a Repeater, it will wait for the controller to set the KSV_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_VALID bit. |
| 0 |
R |
AUTHED |
HDCP Authenticated: Indicates the HDCP authentication has completed successfully. The controller may now send video data re-quiring content protection. This bit will be cleared if authentication is lost or if the controller restarts authen-tication. |
| 198 |
0xC6 |
ICR |
7 |
RW |
0x00 |
IE_IND_ACC |
Interrupt on Indirect Access Complete: Enables interrupt on completion of Indirect Register Access. |
| 6 |
RW |
IE_RXDET_INT |
Interrupt on Receiver Detect: Enables interrupt on detection of a downstream Receiver. If HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect. |
| 5 |
RW |
IE_RX_INT |
Interrupt on Receiver interrupt: Enables interrupt on indication from the HDCP Receiver. Allows propagation of interrupts from downstream devices. |
| 4 |
RW |
0x00 |
IE_LIST_RDY |
Interrupt on KSV List Ready: Enables interrupt on KSV List Ready. |
| 3 |
RW |
IE_KSV_RDY |
Interrupt on KSV Ready: Enables interrupt on KSV Ready. |
| 2 |
RW |
IE_AUTH_FAIL |
Interrupt on Authentication Failure: Enables interrupt on authentication failure or loss of authentication. |
| 1 |
RW |
IE_AUTH_PASS |
Interrupt on Authentication Pass: Enables interrupt on successful completion of authentication. |
| 0 |
RW |
INT_EN |
Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller. |
| 199 |
0xC7 |
ISR |
7 |
R |
0x00 |
IS_IND_ACC |
Interrupt on Indirect Access Complete: Indirect Register Access has completed. |
| 6 |
R |
IS_RXDET_INT |
Interrupt on Receiver Detect interrupt: A downstream receiver has been detected. If HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect. |
| 5 |
R |
IS_RX_INT |
Interrupt on Receiver interrupt: Receiver has indicated an interrupt request from down-stream device. |
| 4 |
R |
0x00 |
IS_LIST_RDY |
Interrupt on KSV List Ready: The KSV list is ready for reading by the controller. |
| 3 |
R |
IS_KSV_RDY |
Interrupt on KSV Ready: The Receiver KSV is ready for reading by the controller. |
| 2 |
R |
IS_AUTH_FAIL |
Interrupt on Authentication Failure: Authentication failure or loss of authentication has occurred. |
| 1 |
R |
IS_AUTH_PASS |
Interrupt on Authentication Pass: Authentication has completed successfully. |
| 0 |
R |
INT |
Global Interrupt: Set if any enabled interrupt is indicated. |
| 200 |
0xC8 |
NVM_CTL |
7 |
R |
0x00 |
NVM_PASS |
NVM Verify pass: This bit indicates the completion status of the NVM verification process. This bit is valid only when NVM_DONE is asserted.
0: NVM Verify failed.
1: NVM Verify passed. |
| 6 |
R |
NVM_DONE |
NVM Verify done: This bit indicates that the NVM Verifcation has completed. |
| 5 |
RW |
|
Reserved. |
| 4:3 |
R |
|
|
Reserved. |
| 2 |
RW |
0x00 |
NVM_VFY |
NVM Verify: Setting this bit will enable a verification of the NVM con-tents. This is done by reading all NVM keys, computing a SHA-1 hash value, and verifying against the SHA-1 hash stored in NVM. This bit will be cleared upon com-pletion of the NVM Verification. |
| 1 |
RW |
|
Reserved. |
| 0 |
RW |
|
Reserved. |
| 206 |
0xCE |
BLUE_SCREEN |
7:0 |
RW |
0xFF |
BLUE_SCREEN_VAL |
Blue Screen Data Value: Provides the 8-bit data value sent on the Blue channel when the HDCP Transmitter is sending a blue screen. |
| 208 |
0xD0 |
IND_STS |
7 |
RW |
0x00 |
IA_RST |
Indirect Access Reset: Setting this bit to a 1 will reset the I2C Master in the HDCP Receiver. As this may leave the I2C bus in an indeterminate state, it should only be done if the Indirect Access mechanism is not able to complete due to an error on the destination I2C bus. |
| 6 |
RW |
I2C_TO_SPEED |
I2C Timer Speedup: For diagnostic purposes allow speedup of of the 1 second idle timer to 50us. Texas Instruments use only, should be marked as Reserved in datasheet. |
| 5 |
RW |
I2C_TO_DIS |
I2C Timeout Disable: Setting this bit to a 1 will disable the bus timeout function in the I2C master. When enabled, the bus timeout function allows the I2C master to assume the bus is free if no signaling occurs for more than 1 second. |
| 4 |
RW |
I2C_FAST |
I2C Fast mode Enable: Setting this bit to a 1 will enable the I2C Master in the HDCP Receiver to operation with Fast mode timing. If set to a 0, the I2C Master will operation with Standard mode timing. |
| 3:2 |
|
|
|
Reserved. |
| 1 |
R |
0x00 |
IA_ACK |
Indirect Access Acknowledge: The acknowledge bit indicates that a valid acknowledge was received upon completion of the I2C read or write to the slave. A value of 0 indicates the read/write did not complete successfully. |
| 0 |
R |
IA_DONE |
Indirect Access Done: Set to a 1 to indicate completion of Indirect Register Access. This bit will be cleared or read or by start of a new Indirect Register Access. |
| 209 |
0xD1 |
IND_SAR |
7:1 |
RW |
0x00 |
IA_SADDR |
Indirect Access Slave Address: This field should be programmed with the slave address for the I2C slave to be accessed. |
| 0 |
RW |
IA_RW |
Indirect Access Read/Write:
1 = Read.
0 = Write. |
| 210 |
0xD2 |
IND_OAR |
7:0 |
RW |
0x00 |
IA_OFFSET |
Indirect Access Offset: This field should be programmed with the register address for the I2C indirect access. |
| 211 |
0xD3 |
IND_DATA |
7:0 |
RW |
0x00 |
IA_DATA |
Indirect Access Data: For an indirect write, this field should be written with the write data. For an indirect read, this field will contain the result of a successful read. |
| 224 |
0xE0 |
HDCP_DBG_ALIAS |
7:0 |
R |
|
HDCP_DBG |
Read-only alias of HDCP_DBG register. |
| 226 |
0xE2 |
HDCP_CFG_ALIAS |
7:0 |
R |
|
HDCP_CFG |
Read-only alias of HDCP_CFG register. |
| 227 |
0xE3 |
HDCP_CTL_ALIAS |
7:0 |
R |
|
HDCP_CTL |
Read-only alias of HDCP_CTL register. |
| 228 |
0xE4 |
HDCP_STS_ALIAS |
7:0 |
R |
|
HDCP_STS |
Read-only alias of HDCP_STS register. |
| 230 |
0xE6 |
HDCP_ICR_ALIAS |
7:0 |
R |
|
HDCP_ICR |
Read-only alias of HDCP_ICR register. |
| 231 |
0xE7 |
HDCP_ISR_ALIAS |
7:0 |
R |
|
HDCP_ISR |
Read-only alias of HDCP_ISR register. |
| 240 |
0xF0 |
TX ID |
7:0 |
R |
0x5F |
ID0 |
First byte ID code: "_". |
| 241 |
0xF1 |
7:0 |
R |
0x55 |
ID1 |
Second byte of ID code: "U". |
| 242 |
0xF2 |
7:0 |
R |
0x48 |
ID2 |
Third byte of ID code: "H". |
| 243 |
0xF3 |
7:0 |
R |
0x39 |
ID3 |
Fourth byte of ID code: "9". |
| 244 |
0xF4 |
7:0 |
R |
0x34 |
ID4 |
Fifth byte of ID code: "4". |
| 245 |
0xF5 |
7:0 |
R |
0x37 |
ID5 |
Sixth byte of ID code: “7”. |