ZHCSD37A November 2014 – March 2019 DS90UH947-Q1
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | PIN/FREQ. | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| GPIO FREQUENCY(3) | |||||||
| Rb,FC | Forward Channel GPIO Frequency | Single-Lane, CLK = 25 MHz - 96 MHz | GPIO[3:0], D_GPIO[3:0] | 0.25 × CLK | MHz | ||
| Dual-Lane, CLK/2 = 25 MHz - 85 MHz | 0.125 × CLK | ||||||
| tGPIO,FC | GPIO Pulse Width, Forward Channel | Single-Lane, CLK = 25 MHz - 96 MHz | GPIO[3:0], D_GPIO[3:0] | >2 / CLK | s | ||
| Dual-Lane, CLK/2 = 25 MHz - 85 MHz | >2 / (CLK/2) | ||||||
| OpenLDI INPUTS | |||||||
| ITJIT(4) | Input Total Jitter Tolerance | Jitter frequency ≤ CLK/40 | CLK±, D[7:0]± | 0.2 | UIOLDI(1) | ||
| FPD-LINK III OUTPUT | |||||||
| tLHT | Low Voltage Differential Low-to-High Transition Time | 80 | ps | ||||
| tHLT | Low Voltage Differential High-to-Low Transition Time | 80 | ps | ||||
| tXZD | Output Active to OFF Delay | PDB = L | 100 | ns | |||
| tPLD | Lock Time (OpenLDI Rx) | 5 | ms | ||||
| tSD | Delay — Latency | CLK± | 294 | T(5) | |||
| tDJIT | Output Total Jitter(Figure 6 ) | Random Pattern | Single-Lane: High pass filter CLK/20 | 0.3 | UIFPD3(2) | ||
| Dual-lane: High pass filter CLK/40 | |||||||
| λSTXBW | Jitter Transfer Function (-3-dB Bandwidth) | 1 | MHz | ||||
| δSTX | Jitter Transfer Function Peaking | 0.1 | dB | ||||