8.3.1 High Speed Forward Channel Data Transfer

The High Speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, HDCP, I²C, and I2S audio transmitted from serializer to deserializer. Figure 19 illustrates the serial stream PCLK cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, DC-balanced and scrambled.

Figure 19. FPD-Link III Serial Stream

The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 85 MHz (LFMODE=0). This corresponds to an application payload rate range of 155 Mbps to 2.635 Gbps, with an actual line rate range of 525 Mbps to 2.975 Gbps.

8.3.2 Low Speed Back Channel Data Transfer

The Low-Speed Back Channel of the DS90UH928Q-Q1 provides bidirectional communication between the display and host processor. The back channel control data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock information. Together, the forward channel and back channel for the bidirectional control channel (BCC). This architecture provides a backward path across the serial link together with a high speed forward channel. The back channel contains the I²C, HDCP, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.

8.3.3 Backward Compatible Mode

The DS90UH928Q-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q for PCLK frequencies ranging from 15 MHz to 65 MHz. The deserializer receives 28-bits of data over a single serial FPD-Link II pair operating at a payload rate of 120 Mbps to 1.8 Gbps, corresponding to a line rate of 140 Mbps to 2.1 Gbps. The Backward Compatibility configuration can be selected through the MODE_SEL pin or programmed through the device control registers (Table 7). The bidirectional control channel, HDCP, bidirectional GPIOs, I2S, and interrupt (INTB) are not active in this mode. However, local I²C access to the serializer is still available. Note: PCLK frequency range in this mode is 15 MHz to 65 MHz for LFMODE=0 and 5 MHZ to <15 MHz for LFMODE=1.

8.3.4 Input Equalization

An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces medium-induced deterministic jitter. It equalizes up to 10m STP cables with 3 connection breaks at maximum serializer stream payload rate of 2.975 Gbps.

The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 5). This mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value stored in the control registers (Table 7).

8.3.5 Common Mode Filter Pin (CMF)

The deserializer provides access to the center tap of the internal CML termination. A 0.1-μF capacitor must be connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 39). This increases noise rejection capability in high-noise environments.

8.3.6 Power Down (PDB)

The deserializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an external device, or through V_DDIO, where V_DDIO = 3.0 V to 3.6 V or V_DD33. To save power, disable the link when the display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before V_DD33 and V_DDIO have reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before releasing or driving high (See Recommended Operating Conditions). In the case where PDB is pulled up to V_DDIO = 3.0 V to 3.6 V or V_DD33 directly, a 10-kΩ pullup resistor and a >10-µF capacitor to ground are required (See Figure 39 ).

Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time, PDB must be held low for a minimum of 2 ms (See AC Electrical Characteristics).

8.3.7 Video Control Signals

The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations relative to the video pixel clock period (PCLK). By default, the device applies a minimum pulse width filter on these signals to help eliminate spurious transitions.

Normal Mode Control Signals (VS, HS, DE) have the following restrictions:

• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 7. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this restriction (minimum is 1 PCLK). See Table 7. DE can have at most two transitions per 130 PCLKs.

8.3.8 EMI Reduction Features

8.3.9 Built In Self Test (BIST)

An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and the low-speed back channel without external data connections. This is useful in the prototype stage, equipment production, in-system test, and system diagnostics.

8.3.9.1 BIST Configuration and Status

The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may select either an external PCLK or the 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration register.

When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel frame.

The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.

See Figure 20 for the BIST mode flow diagram.

8.3.9.1.1 Sample BIST Sequence

1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate.
3. To Stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If there one or more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may be of any length.

The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing signal condition enhancements (Rx Equalization).

Figure 20. BIST Mode Flow Diagram

8.3.9.2 Forward Channel and Back Channel Error Checking

The deserializer, on locking to the serial stream, compares the recovered serial stream with all-zeroes and records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer. Forward channel errors may also be read from register 0x25 (Table 7).

The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream, as indicated by link detect status (register bit 0x0C[0] - Table 7). CRC errors are recorded in an 8-bit register in the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or the serializer enters BIST mode again.

Figure 21. BIST Waveforms

8.3.10 Internal Pattern Generation

The DS90UH928Q-Q1 deserializer features an internal pattern generator. It allows basic testing and debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to TI Application Note: ().

8.3.11 Image Enhancement Features

Several image enhancement features are provided. The White Balance LUTs allow the user to define and map the color profile of the display. Adaptive Hi-FRC Dithering enables the presentation of 'true color' images on an 18-bit display.

8.3.11.1 White Balance

The White Balance feature enables similar display appearance when using LCD’s from different vendors. It compensates for native color temperature of the display, and adjusts relative intensities of R, G, and B to maintain specified color temperature. Programmable control registers are used to define the contents of three LUTs (8-bit color value for Red, Green and Blue) for the White Balance Feature. The LUTs map input RGB values to new output RGB values. There are three LUTs, one LUT for each color. Each LUT contains 256 entries, 8-bits per entry with a total size of 6144 bits (3 x 256 x 8). All entries are readable and writable. Calibrated values are loaded into registers through the I2C interface (deserializer is a slave device). This feature may also be applied to lower color depth applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured via serial control bus register.

8.3.11.1.1 LUT Contents

The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3 tables. Unused bits - LSBs -shall be set to “0” by the user.

When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique 8-bit entries. The 8-bit white balanced data is then available at the output of the deserializer, and driven to the display.

The user must define and load the contents of the LUT for each color (R,G,B). Regardless of the color depth being driven (888, 666, 656), the user must always provide contents for 3 complete LUTs - 256 colors x 8 bits x 3 tables. Unused bits - LSBs -shall be set to “0” by the user. When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique 8-bit entries. The 8-bit white balanced data is then available at the output of the deserializer, and driven to the display.

Alternatively, with 6-bit input data the user may choose to load complete 8-bit values into each LUT. This mode of operation provides the user with finer resolution at the LUT output to more closely achieve the desired white point of the calibrated display. Although 8-bit data is loaded, only 64 unique 8-bit white balance output values are available for each color (R, G and B). The result is 8-bit white balanced data. Before driving to the output of the deserializer, the 8-bit data must be reduced to 6-bit with an FRC dithering function. To operate in this mode, the user must configure the deserializer to enable the FRC2 function.

Examples of the three types of LUT configurations described are shown in Figure 22.

8.3.11.1.2 Enabling White Balance

The user must load all 3 LUTs prior to enabling the white balance feature. The following sequence must be followed by the user.

To initialize white balance after power-on:

1. Load contents of all 3 LUTs . This requires a sequential loading of LUTs - first RED, second GREEN, third BLUE. 256, 8-bit entries must be loaded to each LUT. Page registers must be set to select each LUT.
2. Enable white balance. By default, the LUT data may not be reloaded after initialization at power-on.

An option does exist to allow LUT reloading after power-on and initial LUT loading (as described above). This option may only be used after enabling the white balance reload feature via the associated serial control bus register. In this mode the LUTs may be reloaded by the master controller via I2C. This provides the user with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set of LUT values. The host controller loads the updated LUT values via the serial bus interface. There is no need to disable the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be seamless - no interruption of displayed data.

It is important to note that initial loading of LUT values requires that all 3 LUTs be loaded sequentially. When reloading, partial LUT updates may be made.

Figure 22. White Balance LUT Configuration

8.3.11.2 Adaptive Hi-FRC Dithering

The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits per sub-pixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color gradients, and allowing the flexibility to use lower cost 18-bit displays. FRC (Frame Rate Control) dithering is a method to emulate “missing” colors on a lower color depth LCD display by changing the pixel color slightly with every frame. FRC is achieved by controlling on and off pixels over multiple frames (Temporal). Static dithering regulates the number of on and off pixels in a small defined pixel group (Spatial). The FRC module includes both Temporal and Spatial methods and also Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full (16,777,216) color on an 18-bit LCD panel. The “adaptive” FRC module also includes input pixel detection to apply specific Spatial dithering methods for smoother gray level transitions. When enabled, the lower LSBs of each RGB output are not active; only 18 bit data (6 bits per R,G and B) are driven to the display. This feature is enabled via serial control bus register. Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance LUT, and is intended to be used when 24-bit data is being driven to an 18-bit display with a white balance LUT that is calibrated for an 18-bit data source. The second FRC block, RC2, follows the white balance block and is intended to be used when fine adjustment of color temperature is required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT calibrated for 24-bit source data.

For proper operation of the FRC dithering feature, the user must provide a description of the display timing control signals. The timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active polarity of the timing control signals. All this information is entered to device control registers via the serial bus interface.

Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit data. This allows the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is evaluated, and one of four possible algorithms is selected. The majority of incoming data sequences are supported by the default dithering algorithm. Certain incoming data patterns (black/white pixel, full on/off sub-pixel) require special algorithms designed to eliminate visual artifacts associated with these specific gray level transitions. Three algorithms are defined to support these critical transitions.

An example of the default dithering algorithm is illustrated in Figure 23. The 1 or 0 value shown in the table describes whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated LSBs are “001”.

Figure 23. Default FRC Algorithm

8.3.12 Serial Link Fault Detect

The DS90UH928Q-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 7). The device will detect any of the following conditions:

1. Cable open
2. RIN+ to - short
3. RIN+ to GND short
4. RIN- to GND short
5. RIN+ to battery short
6. RIN- to battery short
7. Cable is linked incorrectly (RIN+/RIN- connections reversed)

8.3.13 Oscillator Output

The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost. This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable) Table 7.

8.3.14 Interrupt Pin (INTB)

1. On the serializer, set register (HDCP_ICR) 0xC6[5] = 1 and 0xC6[0] = 1 (Table 7) to configure the interrupt.
2. On the serializer, read from HDCP_ISR register 0xC7 to arm the interrupt for the first time.
3. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
4. The external controller detects INTB = LOW and reads the HDCP_ISR register (Table 7) to determine the interrupt source. Reading this register also clears and resets the interrupt.

8.3.15 General-Purpose I/O

8.3.16 I²S Audio Interface

The DS90UH928Q-Q1 deserializer features six I2S output pins that, when paired with a DS90UH927Q-Q1serializer, supports surround sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1 MHz and the smaller of <PCLK/2 or <13 MHz. Four I2S data outputs carry two channels of I2S-formatted digital audio each, with each channel delineated by the word select (I2C_WC) input. The I²S audio interface is not available in Backwards Compatibility Mode (BKWD = 1).

Figure 24. I2S Connection Diagram

Figure 25. I2S Frame Timing Diagram

When paired with a DS90UH925Q-Q1, the DS90UH928Q-Q1 I2S interface supports a single I2S data output through I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18-bit video mode).

8.4.1 Clock and Output Status

When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW (depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available on the LVCMOS and LVDS outputs. The State of the outputs is based on the OEN and OSS_SEL setting (Table 4) or register bit (Table 7).

8.4.2 FPD-Link Input Frame and Color Bit Mapping Select

The DS90UH928Q-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2 different mapping schemes, shown in Figure 26, or MSBs on TxOUT[3], shown in Figure 27. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock output from TxCLKOUT± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL pin or by Register (Table 7).

Figure 26. 24-bit Color FPD-Link Mapping: LSBs on TxOUT3 (MAPSEL=L)

Figure 27. 24-bit ColorFPD-Link Mapping: MSBs on TxOUT3 (MAPSEL=H)

Figure 28. 18-bit Color FPD-Link Mapping (MAPSEL = L)

Figure 29. 18-bit Color FPD-Link Mapping (MAPSEL = H)

8.4.3 Low Frequency Optimization (LFMODE)

The LFMODE is set via register (Table 7) or by the LFMODE Pin. This mode optimizes device operation for lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE=0, default), the TxCLKOUT± PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High (LFMODE=1), the TxCLKOUT± frequency is between 5 MHz and <15 MHz. Note: when the device LFMODE is changed, a PDB reset is required. When LFMODE is high (LFMODE=1), the line rate relative to the input data rate is multiplied by four. Thus, for the operating range of 5 MHz to <15 MHz, the line rate is 700 Mbps to <2.1 Gbps with an effective data payload of 175 Mbps to 525 Mbps. Note: for Backwards Compatibility Mode (BKWD=1), the line rate relative to the input data rate remains the same.

8.4.4 Mode Select (MODE_SEL)

Device configuration may be done via the MODE_SEL pin or via register (Table 7). A pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (VR4) and V_DD33 to select one of the 9 possible selected modes. See Figure 30 and Table 5.

Figure 30. MODE_SEL Connection Diagram

8.4.5 Repeater Connections

The HDCP Repeater requires the following connections between the HDCP Receiver and each HDCP Transmitter Figure 31.

1. Video Data – Connect all FPD-Link data and clock pairs
2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to V_DD33 or V_DDIO = 3.0 V to 3.6 V with 4.7-kΩ resistors.
3. Audio (optional) – Connect I2S_CLK, I2S_WC, and I2S_Dx signals.
4. IDx pin – Each Transmitter and Receiver must have an unique I2C address.
5. REPEAT & MODE_SEL pins — All Transmitters and Receivers must be set into Repeater Mode.
6. Interrupt pin – Connect DS90UH928Q-Q1 INTB_IN pin to the DS90UH927Q-Q1 INTB pin. The signal must be pulled up to V_DDIO with a 10-kΩ resistor.

Figure 31. HDCP Repeater Connection Diagram

8.4.5.1 Repeater Fan-Out Electrical Requirements

Repeater applications requiring fan-out from one DS90UH928Q-Q1 deserializer to up to three DS90UH927Q-Q1 serializers requires special considerations for routing and termination of the FPD-Link differential traces. Figure 32 details the requirements that must be met for each signal pair:

Figure 32. FPD-Link Fan-Out Electrical Requirements

8.4.6 HDCP I2S Audio Encryption

Depending on the quality and specifications of the audiovisual source, HDCP encryption of digital audio may be required. When HDCP is active, packetized Data Island Transport audio is also encrypted along with the video data per HDCP v.1.3. I2S audio transmitted in Forward Channel Frame Transport mode is not encrypted. System designers should consult the specific HDCP specifications to determine if encryption of digital audio is required by the specific application audiovisual source.

8.4.7 Repeater Configuration

The HDCP Cipher function is implemented in the deserializer per HDCP v1.3 specification. The DS90UH928Q-Q1 provides HDCP decryption of audiovisual content when connected to an HDCP capable FPD-Link III serializer. HDCP authentication and shared key generation is performed using the HDCP Control Channel, which is embedded in the forward and backward channels of the serial link. On-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the manufacturing process and are not accessible external to the device.

The supported HDCP Repeater application provides a mechanism to extend HDCP transmission over multiple links to multiple display devices. It authenticates all HDCP devices in the system and distributes protected content to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.

Figure 33. HDCP Maximum Repeater Application

In the HDCP repeater application, this document refers to the DS90UH927Q-Q1 or DS90UH925Q-Q1 as the HDCP Transmitter (TX), and refers to the DS90UH928Q-Q1 or DS90UH926Q-Q1 as the HDCP Receiver (RX). Figure 33 shows the maximum configuration supported for HDCP Repeater implementations. Two levels of HDCP Repeaters are supported with a maximum of three HDCP Transmitters per HDCP Receiver.

In a repeater application, the I²C interface at each TX and RX is configured to transparently pass I²C communications upstream or downstream to any I2C device within the system. This includes a mechanism for assigning alternate IDs (Slave Aliases) to downstream devices in the case of duplicate addresses.

To support HDCP Repeater operation, the RX includes the ability to control the downstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSV list to the upstream HDCP Transmitter. An I²C master within the RX communicates with the I²C slave within the TX. The TX handles authenticating with a downstream HDCP Receiver and makes status available through the I²C interface. The RX monitors the transmit port status for each TX and reads downstream KSV and KSV list values from the TX.

In addition to the I²C interface used to control the authentication process, the HDCP Repeater implementation includes two other interfaces. The FPD-Link LVDS interface outputs the unencrypted video data. In addition to providing the video data, the LVDS interface communicates control information and packetized audio data. All audio and video data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter. Figure 34 provides more detailed block diagram of a 1:2 HDCP repeater configuration.

If the repeater node includes a local output to a display, White Balancing and Hi-FRC dithering functions should not be used as they will block encrypted I2S audio and HDCP authentication.

Figure 34. HDCP 1:2 Repeater Configuration

8.5.1 Serial Control Bus

The DS90UH928Q-Q1 may also be configured by the use of an I²C compatible serial control bus. Multiple devices may share the serial control bus (up to 10 device addresses supported). The device address is set via a resistor divider (R1 and R2 — see Figure 35) connected to the IDx pin.

Figure 35. Serial Control Bus Connection

The serial control bus consists of two signals and an address configuration pin. SCL is a Serial Bus Clock Input/Output. SDA is the Serial Bus Data Input/Output signal. Both SCL and SDA signals require an external pullup resistor to V_DD33 or V_DDIO = 3.0 V to 3.6 V. For most applications, a 4.7-kΩ pullup resistor to V_DD33 is recommended. The signals are either pulled HIGH, or driven LOW.

The IDx pin configures the control interface to one of 10 possible device addresses. A pullup resistor and a pulldown resistor should be used to set the appropriate voltage ratio between the IDx input pin (V_R2) and V_DD33, each ratio corresponding to a specific device address. See Table 7 below.

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 36.

Figure 36. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus LOW. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled HIGH. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 37 and a WRITE is shown in Figure 38.

Figure 37. Serial Control Bus — READ

Figure 38. Serial Control Bus — WRITE

To support I²C transactions over the BCC. the I²C Master located at the DS90UH928Q-Q1 deserializer must support I²C clock stretching. For more information on I²C interface requirements and throughput considerations, please refer to TI Application Note SNLA131.

Table 7. Serial Control Bus Registers⁽¹⁾⁽²⁾