ZHCSDB4B MARCH   2013  – January 2015 DS90UH928Q-Q1

PRODUCTION DATA.  

1. 1 特性
2. 2 應用范圍
3. 3 說明
4. 4 應用圖
5. 5 修訂歷史記錄
6. 6 Pin Configuration and Functions
7. 7 Specifications
   1. 7.1  Absolute Maximum Ratings
   2. 7.2  ESD Ratings
   3. 7.3  Recommended Operating Conditions
   4. 7.4  Thermal Information
   5. 7.5  DC Electrical Characteristics
   6. 7.6  AC Electrical Characteristics
   7. 7.7  Timing Requirements for the Serial Control Bus
   8. 7.8  Timing Requirements
   9. 7.9  DC and AC Serial Control Bus Characteristics
   10. 7.10 Typical Characteristics
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1  High Speed Forward Channel Data Transfer
      2. 8.3.2  Low Speed Back Channel Data Transfer
      3. 8.3.3  Backward Compatible Mode
      4. 8.3.4  Input Equalization
      5. 8.3.5  Common Mode Filter Pin (CMF)
      6. 8.3.6  Power Down (PDB)
      7. 8.3.7  Video Control Signals
      8. 8.3.8  EMI Reduction Features
         1. 8.3.8.1 LVCMOS VDDIO Option
      9. 8.3.9  Built In Self Test (BIST)
         1. 8.3.9.1 BIST Configuration and Status
            1. 8.3.9.1.1 Sample BIST Sequence
         2. 8.3.9.2 Forward Channel and Back Channel Error Checking
      10. 8.3.10 Internal Pattern Generation
          1. 8.3.10.1 Pattern Options
          2. 8.3.10.2 Color Modes
          3. 8.3.10.3 Video Timing Modes
          4. 8.3.10.4 External Timing
          5. 8.3.10.5 Pattern Inversion
          6. 8.3.10.6 Auto Scrolling
          7. 8.3.10.7 Additional Features
      11. 8.3.11 Image Enhancement Features
          1. 8.3.11.1 White Balance
             1. 8.3.11.1.1 LUT Contents
             2. 8.3.11.1.2 Enabling White Balance
          2. 8.3.11.2 Adaptive Hi-FRC Dithering
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Oscillator Output
      14. 8.3.14 Interrupt Pin (INTB)
      15. 8.3.15 General-Purpose I/O
          1. 8.3.15.1 GPIO[3:0]
          2. 8.3.15.2 GPIO[8:5]
      16. 8.3.16 I2S Audio Interface
          1. 8.3.16.1 I2S Transport Modes
          2. 8.3.16.2 I2S Repeater
          3. 8.3.16.3 I2S Jitter Cleaning
          4. 8.3.16.4 MCLK
   4. 8.4 Device Functional Modes
      1. 8.4.1 Clock and Output Status
      2. 8.4.2 FPD-Link Input Frame and Color Bit Mapping Select
      3. 8.4.3 Low Frequency Optimization (LFMODE)
      4. 8.4.4 Mode Select (MODE_SEL)
      5. 8.4.5 Repeater Connections
         1. 8.4.5.1 Repeater Fan-Out Electrical Requirements
      6. 8.4.6 HDCP I2S Audio Encryption
      7. 8.4.7 Repeater Configuration
   5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
   6. 8.6 Register Maps
9. 9 Application and Implementation
   1. 9.1 Application Information
   2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
         1. 9.2.2.1 Transmission Media
         2. 9.2.2.2 Display Application
      3. 9.2.3 Application Curves
10. 10Power Supply Recommendations
11. 11Layout
    1. 11.1 Layout Guidelines
       1. 11.1.1 CML Interconnect Guidelines
    2. 11.2 Layout Example
12. 12器件和文檔支持
    1. 12.1 文檔支持
       1. 12.1.1 相關文檔　
    2. 12.2 商標
    3. 12.3 靜電放電警告
    4. 12.4 術語表
13. 13機械封裝和可訂購信息