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ZHCSCL3 JUNE 2014 DS90UH925AQ-Q1

PRODUCTION DATA.

封裝選項

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		MIN	MAX	UNIT
V_DD33	Supply Voltage	–0.3	+4.0	V
V_DDIO	Supply Voltage	–0.3	+4.0	V
	LVCMOS I/O Voltage	–0.3	V_DDIO + 0.3	V
	Serializer Output Voltage	–0.3	+2.75	V
T_J	Junction Temperature		+150	°C
For soldering specifications: see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range	48 Lead WQFN Package	-65	+150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾	-8	+8	kV
		Charged device model (CDM), per AEC Q100-011	-1.25	+1.25	kV
		Machine Model	-250	+250	V
ESD Rating (IEC 61000-4-2) R_D = 330Ω, C_S = 150pF		Air Discharge (D_OUT+, D_OUT-)	-15	+15	kV
ESD Rating (IEC 61000-4-2) R_D = 330Ω, C_S = 150pF		Contact Discharge (D_OUT+, D_OUT-)	-8	+8	kV
ESD Rating (ISO10605) R_D = 330Ω, C_S = 150pF R_D = 2KΩ, C_S = 150pF or 330pF		Air Discharge (D_OUT+, D_OUT-)	-15	+15	kV
		Contact Discharge (D_OUT+, D_OUT-)	-8	+8	kV

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

	MIN	TYP	MAX	UNIT
Supply Voltage (V_DD33)	3.0	3.3	3.6	V
LVCMOS Supply Voltage (V_DDIO)	3.0	3.3	3.6	V
OR
LVCMOS Supply Voltage (V_DDIO)	1.71	1.8	1.89	V
Operating Free Air Temperature (T_A)	−40	+25	+105	°C
PCLK Frequency	5		85	MHz
Supply Noise⁽⁶⁾			100	mV_P-P

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		WQFN	UNIT
THERMAL METRIC⁽¹⁾		48 PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	35	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	5.2
R_θJB	Junction-to-board thermal resistance	5.5
ψ_JT	Junction-to-top characterization parameter	0.1
ψ_JB	Junction-to-board characterization parameter	5.5
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 DC Electrical Characteristics ⁽¹⁾⁽²⁾⁽³⁾

Over recommended operating supply and temperature ranges unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS		PIN/FREQ.	MIN	TYP	MAX	UNIT
LVCMOS I/O DC SPECIFICATIONS
V_IH	High Level Input Voltage	V_DDIO = 3.0 to 3.6 V		PDB	2.0		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3.0 to 3.6 V			GND		0.8	V
I_IN	Input Current	V_IN = 0 V or V_DDIO = 3.0 to 3.6 V			−10	±1	+10	μA
V_IH	High Level Input Voltage	V_DDIO = 3.0 to 3.6 V		R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, I2S_CLK, I2S_WC, I2S_DA, I2S_DB	2.0		V_DDIO	V
V_IH	High Level Input Voltage	V_DDIO = 1.71 to 1.89 V			0.65* V_DDIO		V_DDIO	V
V_IL	Low Level Input Voltage	V_DDIO = 3.0 to 3.6 V			GND		0.8	V
V_IL	Low Level Input Voltage	V_DDIO = 1.71 to 1.89 V			GND		0.35* V_DDIO	V
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 3.0 to 3.6 V		−10	±1	+10	μA
I_IN	Input Current	V_IN = 0 V or V_DDIO	V_DDIO = 1.71 to 1.89 V		−10	±1	+10	μA
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 3.0 to 3.6 V	GPIO[3:0], GPO_REG[7:4], REM_INTB	2.4		V_DDIO	V
V_OH	High Level Output Voltage	I_OH = −4 mA	V_DDIO = 1.71 to 1.89 V		V_DDIO - 0.45		V_DDIO	V
V_OL	Low Level Output Voltage	I_OL = +4 mA	V_DDIO = 3.0 to 3.6 V		GND		0.4	V
V_OL	Low Level Output Voltage	I_OL = +4 mA	V_DDIO = 1.71 to 1.89 V		GND		0.35	V
I_OS	Output Short Circuit Current	V_OUT = 0 V				−50		mA
I_OZ	TRI-STATE® Output Current	V_OUT = 0 V or V_DDIO, PDB = L,			−10		+10	μA
FPD-LINK III CML DRIVER DC SPECIFICATIONS
V_ODp-p	Differential Output Voltage (DOUT+) – (DOUT-)	R_L = 100 Ω, Figure 1		DOUT+, DOUT-	1160	1250	1340	mVp-p
ΔV_OD	Output Voltage Unbalance					1	50	mV
V_OS	Offset Voltage – Single-ended	R_L = 100 Ω, Figure 1				2.5-0.25*V_{ODp-p (TYP)}		V
ΔV_OS	Offset Voltage Unbalance Single-ended					1	50	mV
I_OS	Output Short Circuit Current	DOUT+/- = 0 V, PDB = L or H				−38		mA
R_T	Internal Termination Resistor - Single ended				40	52	62	Ω
SUPPLY CURRENT
I_DD1	Supply Current (includes load current) R_L = 100 Ω, f = 85 MHz	Checker Board Pattern, Figure 2	V_DD33= 3.6 V	V_DD33		148	170	mA
I_DDIO1			V_DDIO = 3.6 V	V_DDIO		90	180	μA
I_DDIO1			V_DDIO = 1.89 V	V_DDIO		1	1.6	mA
I_DDS1	Supply Current Remote Auto Power Down Mode	0x01[7] = 1, deserializer is powered down	V_DD33 = 3.6 V	V_DD33		1.2	2.4	mA
I_DDIOS1			V_DDIO = 3.6 V	V_DDIO		65	150	μA
I_DDIOS1			V_DDIO = 1.89 V	V_DDIO		55	150	μA
I_DDS2	Supply Current Power Down	PDB = L, All LVCMOS inputs are floating or tied to GND	V_DD33 = 3.6 V	V_DD33		1	2	mA
I_DDIOS2			V_DDIO = 3.6 V	V_DDIO		65	150	μA
I_DDIOS2			V_DDIO = 1.89 V	V_DDIO		50	150	μA

7.6 AC Electrical Characteristics⁽¹⁾⁽²⁾⁽³⁾

Over recommended operating supply and temperature ranges unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
GPIO BIT RATE
B_R	Forward Channel Bit Rate	See⁽⁷⁾⁽⁸⁾	f = 5 – 85 MHz GPIO[3:0]		0.25* f		Mbps
B_R	Back Channel Bit Rate	See⁽⁷⁾⁽⁸⁾	f = 5 – 85 MHz GPIO[3:0]		75		kbps
RECOMMENDED TIMING FOR PCLK
t_TCP	PCLK Period	See⁽⁷⁾⁽⁸⁾	PCLK	11.76	T	200	ns
t_CIH	PCLK Input High Time			0.4*T	0.5*T	0.6*T	ns
t_CIL	PCLK Input Low Time			0.4*T	0.5*T	0.6*T	ns
t_CLKT	PCLK Input Transition Time Figure 3⁽⁷⁾⁽⁸⁾		f = 5 MHz	4.0			ns
t_CLKT	PCLK Input Transition Time Figure 3⁽⁷⁾⁽⁸⁾		f = 85 MHz	0.5			ns
t_IJIT	PCLK Input Jitter Tolerance, Bit Error Rate ≤10^-10	f / 40 < Jitter Freq < f / 20⁽⁷⁾⁽⁹⁾	f = 5 – 78 MHz	0.4	0.6		UI

7.7 Recommended Timing for the Serial Control Bus

Over 3.3 V supply and temperature ranges unless otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	MIN	MAX	UNIT
f_SCL	SCL Clock Frequency	Standard Mode	0	100	kHz
f_SCL	SCL Clock Frequency	Fast Mode	0	400	kHz
t_LOW	SCL Low Period	Standard Mode	4.7		us
t_LOW	SCL Low Period	Fast Mode	1.3		us
t_HIGH	SCL High Period	Standard Mode	4.0		us
t_HIGH	SCL High Period	Fast Mode	0.6		us
t_HD;STA	Hold time for a start or a repeated start condition Figure 8	Standard Mode	4.0		us
t_HD;STA		Fast Mode	0.6		us
t_SU:STA	Set Up time for a start or a repeated start condition Figure 8	Standard Mode	4.7		us
t_SU:STA		Fast Mode	0.6		us
t_HD;DAT	Data Hold Time Figure 8	Standard Mode	0	3.45	us
t_HD;DAT	Data Hold Time Figure 8	Fast Mode	0	0.9	us
t_SU;DAT	Data Set Up Time Figure 8	Standard Mode	250		ns
t_SU;DAT	Data Set Up Time Figure 8	Fast Mode	100		ns
t_SU;STO	Set Up Time for STOP Condition, Figure 8	Standard Mode	4.0		us
t_SU;STO	Set Up Time for STOP Condition, Figure 8	Fast Mode	0.6		us
t_BUF	Bus Free Time Between STOP and START, Figure 8	Standard Mode	4.7		us
t_BUF	Bus Free Time Between STOP and START, Figure 8	Fast Mode	1.3		us
t_r	SCL & SDA Rise Time, Figure 8	Standard Mode		1000	ns
t_r	SCL & SDA Rise Time, Figure 8	Fast Mode		300	ns
t_f	SCL & SDA Fall Time, Figure 8	Standard Mode		300	ns
t_f	SCL & SDA Fall Time, Figure 8	Fast mode		300	ns

7.8 DC and AC Serial Control Bus Characteristics

Over 3.3 V supply and temperature ranges unless otherwise specified.⁽¹⁾⁽²⁾⁽³⁾

SYMBOL	PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input High Level	SDA and SCL	0.7* V_DD33		V_DD33	V
V_IL	Input Low Level Voltage	SDA and SCL	GND		0.3* V_DD33	V
V_HY	Input Hysteresis			>50		mV
V_OL		SDA, IOL = 1.25 mA	0		0.36	V
I_in		SDA or SCL, Vin = V_DD33 or GND	-10		+10	µA
t_R	SDA RiseTime – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 8		430		ns
t_F	SDA Fall Time – READ	SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 8		20		ns
t_SU;DAT	Set Up Time – READ	Figure 8		560		ns
t_HD;DAT	Hold Up Time – READ	Figure 8		615		ns
t_SP	Input Filter			50		ns
C_in	Input Capacitance	SDA or SCL		<5		pF

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.

(2) Typical values represent most likely parametric norms at V_DD = 3.3 V, Ta = +25ºC, and at the Recommended Operation Conditions at the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

(4) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.

(5) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1/35*PCLK). The UI scales with PCLK frequency.

(6) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V_DD33 and V_DDIOsupplies with amplitude = 100 mVp-p measured at the device V_DD33 and V_DDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

(7) Specification is ensured by characterization and is not tested in production.

(8) Specification is ensured by design and is not tested in production.

(9) Jitter Frequency is specified in conjunction with DS90UH926 PLL bandwidth.

7.9 AC Timing Diagrams and Test Circuits

Figure 1. Serializer VOD DC Output

Figure 2. Checkboard Data Pattern

Figure 3. Serializer Input Clock Transition Time

Figure 4. Serializer CML Output Load and Transition Time

Figure 5. Serializer Setup and Hold Times

Figure 6. Serializer Lock Time

Figure 7. Serializer CML Output Jitter

Figure 8. Serial Control Bus Timing Diagram

7.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

SYMBOL	PARAMETER	TEST CONDITIONS	PIN/FREQ.	MIN	TYP	MAX	UNIT
t_LHT	CML Output Low-to-High Transition Time	See Figure 4	DOUT+, DOUT-		80	130	ps
t_HLT	CML Output High-to-Low Transition Time	See Figure 4	DOUT+, DOUT-		80	130	ps
t_DIS	Data Input Setup to PCLK	See Figure 5	R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, I2S_CLK, I2S_WC, I2S_DA	2.0			ns
t_DIH	Data Input Hold from PCLK	See Figure 5		2.0			ns
t_PLD	Serializer PLL Lock Time	Figure 6⁽⁴⁾	f = 15 - 45MHz		131*T		ns
t_SD	Delay — Latency		f = 15 - 45MHz		145*T		ns
t_TJIT	Output Total Jitter, Bit Error Rate ≥10^-10 Figure 7⁽⁷⁾⁽⁸⁾⁽⁵⁾	R_L = 100Ω f = 45MHz	DOUT+, DOUT-		0.25	0.30	UI

7.11 Typical Characteristics

Note: On the rising edge of each clock period, the CML driver outputs a low Stop bit, high Start bit, and 33 DC-scrambled data bits.

Figure 9. Serializer CML Driver Output at 2.73 Gbps

Figure 10. Comparison of Deserializer LVCMOS RX PCLK Output locked to a 78 MHz TX PCLK