7.6.1.43 PCLK_Test_Mode Register (Address = 2Eh) [reset = 0h]
PCLK_Test_Mode is described in Table 54.
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Table 54. PCLK_Test_Mode Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 7 |
EXTERNAL_PCLK |
R/W |
0h |
Select pixel clock from BISTC input. |
| 6-0 |
RESERVED |
R/W |
0h |
Reserved |