7.6.1.29 General_Status Register (Address = 1Ch) [reset = 0h]
General_Status is described in Table 40.
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Table 40. General_Status Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 7-6 |
RESERVED |
R |
0h |
Reserved |
| 5 |
RESERVED |
R |
1h |
Reserved |
| 4 |
DUAL_RX_STS |
R |
0h |
Receiver Dual Link Status.
This bit indicates the current operating mode of the FPD-Link III Receive port.
1: Dual-link mode active
0: Single-link mode active |
| 3 |
I2S_LOCKED |
R |
0h |
I2S LOCK STATUS.
0: I2S PLL controller not locked
1: I2S PLL controller locked to input I2S clock |
| 2 |
RESERVED |
R |
0h |
Reserved |
| 1 |
RESERVED |
R |
0h or 1h |
Reserved |
| 0 |
LOCK |
R |
0h |
De-Serializer CDR, PLL's clock to recovered clock frequency.
1: De-Serializer locked to recovered clock
0: De-Serializer not locked
In Dual-link mode, this indicates both channels are locked. |