ZHCSEN9A NOVEMBER 2014 – January 2016 DS90UB940-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 應用 圖
- 5 修訂歷史記錄
- 6 Pin Configurations and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings—JEDEC
- 7.3 ESD Ratings—IEC and ISO
- 7.4 Recommended Operating Conditions
- 7.5 Thermal Information
- 7.6 DC Electrical Characteristics
- 7.7 AC Electrical Characteristics
- 7.8 Timing Requirements for the Serial Control Bus
- 7.9 Switching Characteristics
- 7.10 Timing Diagrams and Test Circuits
- 7.11 Power Sequence
- 7.12 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 High Speed Forward Channel Data Transfer
- 8.3.2 Low Speed Back Channel Data Transfer
- 8.3.3 FPD-Link III Port Register Access
- 8.3.4 Clock and Output Status
- 8.3.5 LVCMOS VDDIO Option
- 8.3.6 Power Down (PDB)
- 8.3.7 Interrupt Pin — Functional Description and Usage (INTB_IN)
- 8.3.8 General-purpose I/O
- 8.3.9 SPI Communication
- 8.3.10 Backward Compatibility
- 8.3.11 Input Equalization
- 8.3.12 I2S Audio Interface
- 8.3.13 Built-In Self Test (BIST)
- 8.3.14 Internal Pattern Generation
- 8.4 Device Functional Modes
- 8.5
Programming
- 8.5.1 Serial Control Bus
- 8.5.2 Multi-Master Arbitration Support
- 8.5.3 I2C Restrictions on Multi-Master Operation
- 8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
- 8.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
- 8.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configurations and Functions
NKD
64-Pin WQFN
Top View
Pin Functions
| PIN | I/O, TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NUMBER | ||
| MIPI DPHY / CSI-2 OUTPUT PINS - Layout note: for unused CSI outputs, float those pins (do not connect to an external pullup or pulldown) | |||
| CSI0_CLK- CSI0_CLK+ |
21 22 |
O, DPHY | CSI0 Differential clock |
| CSI0_D0- CSI0_D0+ |
23 24 |
O, DPHY | CSI0 Differential pair 0 |
| CSI0_D1- CSI0_D1+ |
25 26 |
O, DPHY | CSI0 Differential pair 1 |
| CSI0_D2- CSI0_D2+ |
27 28 |
O, DPHY | CSI0 Differential pair 2 |
| CSI0_D3- CSI0_D3+ |
29 30 |
O, DPHY | CSI0 Differential pair 3 |
| CSI1_CLK- CSI1_CLK+ |
34 35 |
O, DPHY | CSI1 Differential clock |
| CSI1_D0- CSI1_D0+ |
36 37 |
O, DPHY | CSI1 Differential pair 1 |
| CSI1_D1- CSI1_D1+ |
38 39 |
O, DPHY | CSI1 Differential pair 2 |
| CSI1_D2- CSI1_D2+ |
40 41 |
O, DPHY | CSI1 Differential pair 3 |
| CSI1_D3- CSI1_D3+ |
42 43 |
O, DPHY | CSI1 Differential pair 3 |
| FPD-LINK III INTERFACE - Layout note: for unused FPD-LinkIII inputs, float those pins (do not connect to an external pullup or pulldown) | |||
| RIN0- | 54 | I/O, CML | FPD-Link III Inverting Input/Output The output must be AC-coupled with a 33 nF capacitor. |
| RIN0+ | 53 | I/O, CML | FPD-Link III True Input/Output The output must be AC-coupled with a 33 nF capacitor. |
| RIN1- | 59 | I/O, CML | FPD-Link III Inverting Input/Output The output must be AC-coupled with a 33 nF capacitor. |
| RIN1+ | 58 | I/O, CML | FPD-Link III True Input/Output The output must be AC-coupled with a 33 nF capacitor. |
| CMF | 55 | I/O, CML | Common Mode Filter. Connect 0.1 µF capacitor to GND |
| I2C PINS | |||
| I2C_SDA | 46 | I/O, Open-Drain | I2C Data Input / Output interface Open drain. Must have an external pull-up resistor to VDDIO DO NOT FLOAT. Recommended pull-up: 4.7 kΩ. |
| I2C_SCL | 45 | I/O, Open-Drain | I2C Clock Input / Output Interface Open drain. Must have an external pull-up resistor to VDDIO DO NOT FLOAT. Recommended pull-up: 4.7 kΩ. |
| IDx | 47 | I, Analog Configuration Pin |
Analog input. I2C Serial Control Bus Device ID Address. Table 11 |
| SPI PINS (Pin function programmed through register) - Layout note: for unused SPI pins, tie to an external pulldown | |||
| MOSI (D_GPIO0) |
19 | Multi-function pin I/O, LVCMOS w/ weak internal PD |
Master Out, Slave In. (Pin is shared with D_GPIO0) |
| MISO (D_GPIO1) |
18 | Multi-function pin I/O, LVCMOS w/ weak internal PD |
Master In, Slave Out. (Pin is shared with D_GPIO1) |
| SPLK (D_GPIO2) |
17 | Multi-function pin I/O, LVCMOS w/ weak internal PD |
Serial clock. (Pin is shared with D_GPIO2) |
| SS (D_GPIO3) |
16 | Multi-function pin I/O, LVCMOS w/ weak internal PD |
Slave select. (Pin is shared with D_GPIO3) |
| CONTROL PINS | |||
| MODE_SEL0 | 61 | I, Analog Configuration Pin |
Analog input. Mode Select 0. Connect to external pull-up to VDD33 and pull-down to GND to create a voltage divider. See Table 8 |
| MODE_SEL1 | 50 | I, Analog Configuration Pin |
Analog input. Mode Select 1. Connect to external pull-up to VDD33 and pull-down to GND to create a voltage divider. See Table 9 |
| PDB | 48 | I, LVCMOS Configuration Pin w/ weak internal PD |
Power-Down Mode Input Pin PDB = 1, device is enabled (normal operation) PDB = 0, device is powered down. When the device is in the POWER DOWN state, the LVCMOS outputs are in tri-state, the PLL is shutdown and IDD is minimized. Note: PDB pin requires minimum ramp time of 200us |
| BISTEN | 5 | I, LVCMOS Configuration Pin w/ weak internal PD |
Bist Enable Pin 0: BIST Mode is disabled. 1: BIST Mode is enabled. See Built-In Self Test (BIST) for more information |
| BISTC (INTB_IN) |
4 | I, LVCMOS Configuration Pin w/ weak internal PD |
Bist Clock Select. 0: PCLK 1: 33MHz (Pin is shared with INTB_IN) |
| INTB_IN (BISTC) |
4 | I, LVCMOS w/ weak internal PD |
Interrupt input. (Pin is shared with BISTC) |
| BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS (default pin function) - Layout note: for unused GPIO(s), tie to an external pulldown | |||
| GPIO0 (SDOUT) |
7 | Multi-function pin I/O, LVCMOS |
BCC GPIO0. default state: logic LOW (Pin is shared with SDOUT) |
| GPIO1 (SWC) |
8 | Multi-function pin I/O, LVCMOS |
BCC GPIO1. default state: logic LOW (Pin is shared with SWC) |
| GPIO2 (I2S_DC) |
10 | Multi-function pin I/O, LVCMOS |
BCC GPIO2. default state: logic LOW (Pin is shared with I2S_DC) |
| GPIO3 (I2S_DD) |
9 | Multi-function pin I/O, LVCMOS |
BCC GPIO3. default state: logic LOW (Pin is shared with I2S_DD) |
| HIGH-SPEED GPIO PINS HIGH-SPEED GPIO PINS (default pin function) - Layout note: for unused D_GPIO(s), tie to an external pulldown | |||
| D_GPIO0 (MOSI) |
19 | I/O, LVCMOS | General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with MOSI) |
| D_GPIO1 (MISO) |
18 | I/O, LVCMOS | General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with MISO) |
| D_GPIO2 (SPLK) |
17 | I/O, LVCMOS | General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with SPLK) |
| D_GPIO3 (SS) |
16 | I/O, LVCMOS | General Purpose I/O in 2-lane FPD-Link III mode default state: tri-state (Pin is shared with SS) |
| REGISTER READ/WRITES ONLY GPIO PINS (default pin function) - Layout note: for unused GPIO(s), tie to an external pulldown | |||
| GPIO5_REG (I2S_DB) |
11 | Multi-function pin I/O, LVCMOS |
General Purpose Input/Output 5 I2C register control only. default state: logic LOW (Pin is shared with I2S_DB) |
| GPIO6_REG (I2S_DA) |
12 | Multi-function pin I/O, LVCMOS |
General Purpose Input/Output 6 I2C register control only. default state: logic LOW (Pin is shared with I2S_DA) |
| GPIO7_REG (I2S_WC) |
14 | Multi-function pin I/O, LVCMOS |
General Purpose Input/Output 7 I2C register control only. default state: logic LOW (Pin is shared with I2S_WC) |
| GPIO8_REG (I2S_CLK) |
13 | Multi-function pin I/O, LVCMOS |
General Purpose Input/Output 8 I2C register control only. default state: logic LOW (Pin is shared with I2S_CLK) |
| SLAVE MODE LOCAL I2S CHANNEL PINS (Pin function programmed through register) - Layout note: for unused I2S outputs, tie to an external pulldown | |||
| I2S_WC (GPIO7_REG) |
14 | Multi-function pin O, LVCMOS |
Slave Mode I2S Word Clock Output. (Pin is shared with GPIO7_REG) |
| I2S_CLK (GPIO8_REG) |
13 | Multi-function pin O, LVCMOS |
Slave Mode I2S Clock Output. (Pin is shared with GPIO8_REG) |
| I2S_DA (GPIO6_REG) |
12 | Multi-function pin O, LVCMOS |
Slave Mode I2S Data Output. (Pin is shared with GPIO6_REG) |
| I2S_DB (GPIO5_REG) |
11 | Multi-function pin O, LVCMOS |
Slave Mode I2S Data Output. (Pin is shared with GPIO5_REG) |
| I2S_DC (GPIO2_REG) |
10 | Multi-function pin O, LVCMOS |
Slave Mode I2S Data Output. (Pin is shared with GPIO2) |
| I2S_DD (GPIO3_REG) |
9 | Multi-function pin O, LVCMOS |
Slave Mode I2S Data Output. (Pin is shared with GPIO3) |
| MASTER MODE LOCAL I2S CHANNEL PINS (Pin function programmed through register) - Layout note: for unused GPIO(s), tie to an external pulldown | |||
| SWC (GPIO1) |
8 | Multi-function pin O, LVCMOS |
Master Mode I2S Word Clock Output. (Pin is shared with GPIO1) |
| SDOUT (GPIO0) |
7 | Multi-function pin O, LVCMOS |
Master Mode I2S Data Output. (Pin is shared with GPIO0) |
| MCLK (GPIO9) |
15 | Multi-function pin O, LVCMOS |
Master Mode I2S System Clock Output. (Pin is shared with GPIO9) |
| STATUS PINS - Layout note: add a test point (TP) on these pins | |||
| LOCK | 1 | O, LVCMOS | Lock Status Output LOCK = 1: PLL acquired lock to the reference clock input; DPHY outputs are active LOCK = 0: PLL is unlocked |
| PASS | 7 | O, LVCMOS | Normal mode status output pin (BISTEN = 0) PASS = 1: No fault detected on input display timing PASS = 0: Indicates an error condition or corruption in display timing. Fault condition occurs:
PASS = 1: No error detected PASS = 0: Error detected |
| POWER & GROUND (1) | |||
| VDD33_A, VDD33_B |
56 31 |
Power | 3.3V (±10%) supply. Power to on-chip regulator. Requires 10 µF, 1 µF, 0.1 µF, and 0.01 µF capacitors to GND |
| VDDIO | 3 | Power | LVCMOS I/O power supply, 1.8V (±5%) OR 3.3V (±10%). Requires 10 µF, 1 µF, 0.1 µF, and 0.01 µF capacitors to GND |
| VDD12_CSI0 VDDP12_CSI VDD12_CSI1 VDDL12_0 VDDL12_1 VDDP12_CH0 VDDR12_CH0 VDDP12_CH1 VDDR12_CH1 |
20 32 33 6 44 51 52 60 57 |
Power | 1.2V (±5%) supplies. Requires 10 µF, 1 µF, 0.1 µF, and 0.01 µF capacitors to GND at each VDD pin. |
| CAP_PLL0 CAP_PLL1 CAP_I2S |
49 64 2 |
CAP | Decoupling capacitor connection for on-chip regulator. Each requires a 0.1 µF decoupling capacitor to GND. |
| VSS | DAP | Ground | DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 32 vias. |
| OTHER PINS | |||
| CMLOUTP CMLOUTN |
62 63 |
O, CML | Monitor point for equalized differential signal. Layout recommendation: 1) place 0.1 µF series capacitor on CMLOUTP and CMLOUTN 2) place 100ohm termination between 0.1 µF away from CMLOUTP and CMLOUTN pins 3) place test points from 0.1 µF capacitors |
(1) The VDD (VDD12, VDD33, and VDDIO) supply ramp should be faster than 1.5ms with a monotonic rise