ZHCSEV0 March 2016 DS90UB921-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage – VDD33 | –0.3 | 4 | V | |
| Supply voltage – VDDIO | –0.3 | 4 | V | |
| LVCMOS I/O voltage | –0.3 | VDDIO + 0.3 | V | |
| Serializer output voltage - DOUT± | –0.3 | 2.75 | V | |
| Junction temperature | 150 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±8000 | V |
| Charged-device model (CDM), per AEC Q100-011 | ±1500 | |||
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | RD = 330 Ω, CS = 150 pF | IEC, powered-up only contact discharge (DOUT+, DOUT-) | ±8000 | V |
| IEC, powered-up only air-gap discharge (DOUT+, DOUT-) | ±18000 | ||||
| RD = 330 Ω, CS = 150 and 330 pF | ISO10605 contact discharge (DOUT+, DOUT-) | ±8000 | V | ||
| ISO10605 air-gap discharge (DOUT+, DOUT-) | ±18000 | ||||
| RD = 2 kΩ, CS = 150 and 330 pF | ISO10605 contact discharge (DOUT+, DOUT-) | ±8000 | V | ||
| ISO10605 air-gap discharge (DOUT+, DOUT-) | ±18000 | ||||
| MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|
| Supply voltage (VDD33) | 3 | 3.3 | 3.6 | V |
| LVCMOS supply voltage (VDDIO) | 3 | 3.3 | 3.6 | V |
| 1.71 | 1.8 | 1.89 | V | |
| Operating free-air temperature (TA) | −40 | 25 | 105 | °C |
| PCLK frequency, Coax operation, high frequency mode(1) | 48 | 96 | MHz | |
| PCLK frequency, Coax operation, intermediate frequency mode(1) | 24 | 48 | MHz | |
| PCLK frequency, Coax operation, low frequency mode(1) | 15 | 24 | MHz | |
| PCLK frequency, STP operation, high frequency mode(1) | 15 | 96 | MHz | |
| PCLK frequency, STP operation, low frequency mode(1) | 5 | 15 | MHz | |
| Supply noise -- (DC-50MHz) | 100 | mVP-P |
| THERMAL METRIC(1) | DS90UB921-Q1 | UNIT | |
|---|---|---|---|
| RHS (WQFN) | |||
| 48 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 29 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 11.7 | |
| RθJB | Junction-to-board thermal resistance | 5.0 | |
| ψJT | Junction-to-top characterization parameter | 0.1 | |
| ψJB | Junction-to-board characterization parameter | 6.0 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.7 | |
| PARAMETER | TEST CONDITIONS | PIN/FREQ. | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|---|
| LVCMOS I/O DC SPECIFICATIONS | ||||||||
| VIH | High-level input voltage | VDDIO = 3 V to 3.6 V | PDB | 2 | VDDIO | V | ||
| VIL | Low-level input voltage | VDDIO = 3 V to 3.6 V | GND | 0.8 | V | |||
| IIN | Input current | VIN = 0 V or VIN = VDDIO (3 V to 3.6 V) |
–10 | ±1 | 10 | µA | ||
| VIH | High-level input voltage | VDDIO = 3 V to 3.6 V | DIN[23:0], HS, VS, DE, PCLK, I2S_CLK, I2S_WC, I2S_DA | 2 | VDDIO | V | ||
| VDDIO = 1.71 V to 1.89 V | 0.65 × VDDIO | VDDIO | V | |||||
| VIL | Low-level input voltage | VDDIO = 3 V to 3.6 V | GND | 0.8 | V | |||
| VDDIO = 1.71 V to 1.89 V | GND | 0.35 × VDDIO | V | |||||
| IIN | Input current | VIN = 0 V or VIN = VDDIO |
VDDIO = 3 V to 3.6 V | –10 | ±1 | 10 | µA | |
| VDDIO = 1.71 V to 1.89 V | –10 | ±1 | 10 | µA | ||||
| VOH | High-level output voltage | IOH = –4 mA | VDDIO = 3 V to 3.6 V | GPIO[3:0], GPO_REG[7:4], REM_INTB | 2.4 | VDDIO | V | |
| VDDIO = 1.71 V to 1.89 V | VDDIO – 0.45 | VDDIO | V | |||||
| VOL | Low-level output voltage | IOH = 4 mA | VDDIO = 3 V to 3.6 V | GND | 0.4 | V | ||
| VDDIO = 1.71 V to 1.89 V | GND | 0.35 | V | |||||
| IOS | Output short-circuit current | VOUT = 0 V | –50 | mA | ||||
| IOZ | TRI-STATE output current | VOUT = 0 V or VOUT = VDDIO PDB = L |
–10 | 10 | µA | |||
| FPD-LINK III CML DRIVER DC SPECIFICATIONS | ||||||||
| VOD | Differential output voltage (DOUT+) – (DOUT–) | RL = 100 Ω, see Figure 1 | DOUT± | 700 | 800 | 1000 | mVp-p | |
| VOUT | Single-ended output voltage (DOUT+ or DOUT-) | RL = 50 Ω See Figure 2 |
350 | 400 | 500 | mV | ||
| ΔVOD | Output voltage unbalance | 1 | 50 | mV | ||||
| VOS | Offset voltage — single-ended | RL = 100 Ω See Figure 1 |
2.5 – 0.5 × VOD | V | ||||
| ΔVOS | Offset voltage unbalanced single-ended | 1 | 50 | mV | ||||
| IOS | Output short-circuit current | DOUT± = 0 V, PDB = L or H | –38 | mA | ||||
| RT | Internal termination resistor — single-ended | 40 | 50 | 62 | Ω | |||
| SERIAL CONTROL BUS | ||||||||
| VIH | Input high level, I2C | SDA, SCL | 0.7 × VDD33 | VDD33 | V | |||
| VIL | Input low-level voltage, I2C | 0.3 × VDD33 | V | |||||
| VHY | Input hysteresis, I2C | > 50 | mV | |||||
| VOL | Output Low Level, I2C | IOL = +1.25mA | 0 | 0.36 | V | |||
| IIN | Input Current, I2C | VIN = 0V or VIN = VDD33 |
–10 | 10 | µA | |||
| CIN | Input capacitance, I2C | < 5 | pF | |||||
| SUPPLY CURRENT | ||||||||
| IDD1 | Supply Current (includes load current) RL = 100Ω, f = 96MHz |
Checker Board Pattern, See Figure 3 |
VDD33 = 3.6V | 148 | 180 | mA | ||
| IDDIO1 | VDDIO = 3.6V | 90 | 180 | μA | ||||
| VDDIO = 1.89V | 1 | 3 | mA | |||||
| IDDS1 | Supply Current Remote Auto Power Down Mode | 0x01[7] = 1, deserializer is powered down | VDD33 = 3.6V | 1.2 | 3 | mA | ||
| IDDIOS1 | VDDIO = 3.6V | 65 | 200 | μA | ||||
| VDDIO = 1.89V | 55 | 200 | μA | |||||
| IDDS2 | Supply Current Power Down | PDB = L, All LVCMOS inputs are not connected (NC) or tied to GND | VDD33 = 3.6V | 1 | 3 | mA | ||
| IDDIOS2 | VDDIO = 3.6V | 65 | 200 | μA | ||||
| VDDIO = 1.89V | 55 | 200 | μA | |||||
| IDDS3 | Supply Current Sleep State | 0x01[7] = 1, PCLK is removed. | VDD33 = 3.6V | 55 | mA | |||
| IDDIOS3 | VDDIO = 3.6V | 80 | μA | |||||
| VDDIO = 1.89V | 1 | mA | ||||||
| PARAMETER | TEST CONDITIONS | PIN/FREQUENCY | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| GPIO BIT RATE | |||||||
| BRF | Forward channel bit rate | See(4) | ƒ = 5 – 96 MHz GPIO[3:0] |
0.25 × ƒ | Mbps | ||
| BRB | Back channel bit rate | STP cable - HFMODE | GPIO[3:0] | 60 | kbps | ||
| STP cable - LFMODE Coax cable - HFMODE, IFMODE, or LFMODE |
40 | kbps | |||||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| tTCP | PCLK period with STP cable, see(1)
ƒ = 5 to 96 MHz |
10.41 | T | 200 | ns |
| PCLK period with Coax cable, see(1)
ƒ = 15 to 96 MHz |
10.41 | T | 66.7 | ns | |
| tCIH | PCLK input high time; pin/frequency: PCLK | 0.4*T | 0.5*T | 0.6*T | ns |
| tCIL | PCLK input low time; pin/frequency: PCLK | 0.4*T | 0.5*T | 0.6*T | ns |
| tCLKT | PCLK input transition time(1), see Figure 4; ƒ = 5 MHz | 4 | ns | ||
| PCLK input transition time(1), see Figure 4; ƒ = 96 MHz | 0.5 | ns | |||
| tIJIT | PCLK input jitter, bit error rate ≤ 10–10
ƒ / 40 < jitter freq < ƒ / 20 ƒ = 5 to 78 MHz (1)(2) Paired with DS90UB926Q-Q1 |
0.35 | UI | ||
| PCLK input jitter, bit error rate ≤ 10–10
ƒ / 40 < jitter freq < ƒ / 20 f = 5 - 85MHz (1)(2) Paired with DS90UB928Q-Q1 |
0.35 | UI | |||
| PCLK input jitter, bit error rate ≤ 10–10
ƒ / 40 < jitter freq < ƒ / 20 f = 25 - 96MHz (1)(2) Paired with DS90UB940-Q1, or DS90UB948-Q1 |
0.35 | UI | |||
| MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| ƒSCL | SCL clock frequency | Standard mode | 0 | 100 | kHz | |
| Fast mode | 0 | 400 | kHz | |||
| tLOW | SCL low period | Standard mode | 4.7 | µs | ||
| Fast mode | 1.3 | µs | ||||
| tHIGH | SCL high period | Standard mode | 4 | µs | ||
| Fast mode | 0.6 | µs | ||||
| tHD;STA | Hold time for a start or a repeated start condition, see Figure 10 |
Standard mode | 4 | µs | ||
| Fast mode | 0.6 | µs | ||||
| tSU:STA | Set-up time for a start or a repeated start condition, see Figure 10 |
Standard mode | 4.7 | µs | ||
| Fast mode | 0.6 | µs | ||||
| tHD;DAT | Data hold time, see Figure 10 | Standard mode | 0 | 0.615 | 3.45 | µs |
| Fast mode | 0 | 0.615 | 0.9 | µs | ||
| tSU;DAT | Data set-up time, see Figure 10 | Standard mode | 250 | 0.56 | ns | |
| Fast mode | 100 | 0.56 | ns | |||
| tSU;STO | Set-up time for STOP condition, See Figure 10 |
Standard mode | 4 | µs | ||
| Fast mode | 0.6 | µs | ||||
| tBUF | Bus free time between STOP and START, SeeFigure 10 |
Standard mode | 4.7 | µs | ||
| Fast mode | 1.3 | µs | ||||
| tr | SCL and SDA rise time, See Figure 10 |
Standard mode | 430 | 1000 | ns | |
| Fast mode | 200 | 300 | ns | |||
| tf | SCL and SDA fall time, See Figure 10 |
Standard mode | 20 | 300 | ns | |
| Fast mode | 20 | 300 | ns | |||
| tsp | Input filter | 50 | ns | |||
Figure 1. Serializer Differential VOD DC Output
Figure 2. Serializer Single-ended VOUT DC Output
Figure 3. Checker Board Data Pattern
Figure 4. Serializer Input Clock Transition Time
Figure 5. Serializer CML Output Load and Transition Time
Figure 6. Serializer Setup and Hold Times
Figure 7. Serializer Lock Time
Figure 8. Serializer Delay Time
Figure 9. Serializer CML Output Jitter
Figure 10. Serial Control Bus Timing Diagram
| PARAMETER | TEST CONDITIONS | PIN/FREQ. | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| tLHT | CML Output Low-to-High Transition Time | See Figure 5 | DOUT+, DOUT- | 80 | ps | ||
| tHLT | CML Output High-to-Low Transition Time | 80 | ps | ||||
| tDIS | Data Input Setup to PCLK | See Figure 6 | R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK | 2.0 | ns | ||
| tDIH | Data Input Hold from PCLK | 2.0 | ns | ||||
| tPLD | Serializer PLL Lock Time | See Figure 7 (1) | f = 5 - 96MHz | 131*T | ns | ||
| tSD | Delay — Latency | See Figure 8 | f = 5 - 96MHz | 145*T | ns | ||
| tTJIT | Output Total Intrinsic Jitter, Jitter frequency > f/10 Bit Error Rate ≥10-10 (2) (3) |
RL = 100Ω f = 96MHz See Figure 9 |
DOUT+, DOUT- | 0.25 | 0.30 | UI | |